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Xilinx Virtex-4 ML461 User Manual

Xilinx Virtex-4 ML461 User Manual

Memory interfaces
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Virtex-4 ML461
Memory Interfaces
Development Board
User Guide
UG079 (v1.1) September 5, 2007
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Summary of Contents for Xilinx Virtex-4 ML461

  • Page 1 Virtex-4 ML461 Memory Interfaces Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 2 Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user.
  • Page 3 Updated link to Samsung documentation in Table 4-1 Table 4-3. Chapter 5: Updated Read Data (Q) values in Table 5-5. Appendix A: Updated FPGA pinout tables. General text edits. UG079 (v1.1) September 5, 2007 www.xilinx.com Virtex-4 ML461 Development Board User Guide...
  • Page 4 Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...

  • Page 5: Table Of Contents

    Table of Contents Chapter 1: Introduction About the Virtex-4 ML461 Memory Interfaces Tool Kit ......7 Virtex-4 ML461 Memory Interfaces Development Board .
  • Page 6 UCF Information ............105 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 7: Chapter 1: Introduction

    Xilinx Parallel Cable IV FCRAM-II memory is not supported any longer on the ML461 board. For assistance with any of these items, contact your local Xilinx distributor or visit the Xilinx online store at www.xilinx.com. The heart of the Virtex-4 ML461 Memory Interfaces Tool Kit is the Virtex-4 ML461 Development Board.

  • Page 8: Virtex-4 Ml461 Memory Interfaces Development Board

    Chapter 1: Introduction Virtex-4 ML461 Memory Interfaces Development Board A high-level functional block diagram of the Virtex-4 ML461 Memory Interfaces Development Board is shown in Figure 1-1. External Interfaces: System ACE Controller, ML410 Z-DOK+, LCD SSTL2 SSTL18 HSTL/SSTL18 HSTL FPGA #1...
  • Page 9 Virtex-4 ML461 Memory Interfaces Development Board Figure 1-2 shows the Virtex-4 ML461 Development Board and indicates the locations of the resident memory devices. DDR400 SDRAM DDR2 SDRAM DDR DIMM DDR2 DIMM FCRAM II QDR II SDRAM Display RLDRAM II System ACE...
  • Page 10 Chapter 1: Introduction www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 11: Chapter 2: Getting Started

    “Applying Power to the Board” Documentation and Reference Design CD The CD included in the Virtex-4 ML461 Memory Interfaces Tool Kit contains the design files for the Virtex-4 ML461 Development Board, including schematics, board layout, and reference design files. Open the ReadMe.rtf file on the CD to review the list of contents.

  • Page 12: Applying Power To The Board

    Chapter 2: Getting Started Applying Power to the Board The Virtex-4 ML461 Development Board is now ready to power on. The Virtex-4 ML461 Development Board is shipped with a country-specific AC line cord for the universal input 5V desktop power supply. Follow these steps to power on the Virtex-4 ML461 Development Board: Confirm that the ON-OFF switch, SW4, is in the OFF position.

  • Page 13: Chapter 3: Hardware Description

    Chapter 3 Hardware Description This chapter describes the major hardware blocks on the Virtex-4 ML461 Development Board and provides useful design consideration. It contains the following sections: • “Hardware Overview” • “Memory Interfaces” • “External Interfaces” • “Board Design Considerations”...

  • Page 14: Memory Interfaces

    9:1 data/strobe ratio for the QDR II device. Figure 3-2 illustrates a detailed block diagram of the Virtex-4 ML461 Development Board showing connectivity between the memory types and the four XC4VLX25-FF668 FPGAs.
  • Page 15 FPGA #3 (XC4VLX25-FF668) 448 I/Os ADDR/CNTL 36-Bit FCRAM II ADDR/CNTL 36-Bit Virtex-4 FPGA #4 RLDRAM II (XC4VLX25-FF668) 448 I/Os External Interfaces UG079_c3_02_072905 Figure 3-2: ML461-XC4VLX25-FF668 Board Connectivity Diagram Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...

  • Page 16: Direct Clocking Data Capture Method

    RLDRAM II) is labeled as Direct Clocking method. Refer to XAPP701: “Memory Interfaces Data Capture Using Direct Clocking Technique” for a detailed description. Figure 3-3 shows a basic block diagram for all external memory interfaces on the Virtex-4 ML461 Development Board. Memory Interfaces Board...

  • Page 17: Ddr400 Memory

    Memory Interfaces DDR400 Memory The FPGA #1 device on the Virtex-4 ML461 Development Board is connected to DDR1 memories. The DDR1 memory interface includes: • a 144-bit-wide DIMM connection to two 184-pin DDR1 DIMM sockets • a 28-bit-wide datapath to four DDR400 memory discrete components For the 144-bit-wide DIMM datapath, the data bytes are spread across multiple banks of the FPGA #1 device.
  • Page 18 1. DDR1_DIMM_CKE is connected to a 4.7K pull-down resistor. To use Registered DDR1 DIMMs with the ML461 memory board, it is necessary to connect Pin 10 of socket XP2 (reset#) and drive this signal with FPGA1. www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 19 RTL code are included on the CD shipped with the ML461 Tool Kit. For a complete list of FPGA #1 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.” Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...

  • Page 20: Ddr2 Memory

    Chapter 3: Hardware Description DDR2 Memory The FPGA #2 device on the Virtex-4 ML461 Development Board is connected to DDR2 memories. The DDR2 memory interface includes: • a 144-bit-wide DIMM connection to two 240-pin DDR2 DIMM sockets • a 28-bit-wide datapath to four DDR2 memory discrete components For the 144-bit-wide DIMM datapath, the data bytes are spread across multiple banks of the FPGA #2 device.
  • Page 21 Check Byte 0 DDR2_DIMM_DM_DQS_CB0_7_H_[P,N] DDR2_DIMM_DQ_CB8_15_B[7:0], DDR2 DIMM Data and Strobes: DDR2_DIMM_DQS_CB8_15_L_[P,N], Check Byte 1 DDR2_DIMM_DM_DQS_CB8_15_H_[P,N] Notes: 1. DDR2_DIMM_CKE, DDR2_DIMM_BY0_7_ODT, and DDR2_DIMM_BY8_18_ODT signals are connected to a 4.7K pull-down resistor. Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 22 1. DDR2_CKE and DDR2_ODT signals are connected to a 4.7K pull-down resistor. A copy of XAPP702: "DDR-2 Controller Using Virtex-4 Devices" and its corresponding reference design RTL code are included on the CD shipped with the ML461 Tool Kit. www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 23: Qdr Ii Memories

    Figure 3-6: FPGA #3 Banks for QDR II (HSTL) and FCRAM II (SSTL18) Interfaces (Top View) Table 3-6 describes all the signals associated with QDR II component memories. Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 24 FCR2_DQ_BY[3:2]_B[8:0], FCRAM II Data and Strobes: Bytes 3:2 FCR2_DS_BY2_3, FCR2_QS_BY2_3 For a complete list of FPGA #3 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.” www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 25: Rldram Ii Memory

    Note: Banks 1 & 2 do not have DCI capability due to lack of VRP/VRN. UG079_c3_07_072905 Figure 3-7: FPGA #4 Banks for RLDRAM II (HSTL) Interfaces (Top View) Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 26 RTL code are included on the CD shipped with the ML461 Tool Kit. For a complete list of FPGA #4 signals and their pin locations, refer to Appendix A, “FPGA Pinouts.” www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 27: External Interfaces

    (ICS8430), one per FPGA (SYNTH_CLK_TO_FPGAx_[P,N]). Liquid Crystal Display (LCD) The Virtex-4 ML461 Development Board provides an 8-bit interface to a 64 x 128 LCD panel (DisplayTechQ 64128E-FC-BC-3LP, 64 x 128). The LCD is attached to the board via the receptacle connector P55 and four stand-offs. This display was chosen because of its possible use in embedded systems.

  • Page 28: User Pushbutton Switch

    Table 3-10). There is a pull- up resistor on the pushbutton switch signal on the Virtex-4 ML461 Development Board. The internal FPGA pull-up resistor does not need to be used to force the pushbutton switch signal High when its associated switch is not pressed. Switch contact debounce logic must be implemented inside the FPGA.

  • Page 29: Z-Dok+ Port

    Z-DOK+ Port For an external processor interface, a pair of Z-DOK+ connectors (Tyco 137555-1) are provided (at locations PM1 and PM2). Through these connectors, the Virtex-4 ML461 Development Board can plug into an MLx10-series motherboard developed by the Xilinx APD Systems Engineering Group (SEG).

  • Page 30: Characterization

    Table 3-12: FPGA #4 Signals for Voltage Margining Power Plane Signal Name VCC1V2 VMARGIN_UP_VCC1V2_N VMARGIN_DN_VCC1V2_N SSTL18 VMARGIN_UP_SSTL18_N VMARGIN_DN_SSTL18_N SSTL2 VMARGIN_UP_SSTL2_N VMARGIN_DN_SSTL2_N HSTL VMARGIN_UP_HSTL_N VMARGIN_DN_HSTL_N www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 31 Tying pin 8 (TRACK) of two or more power modules together guarantees that these voltages will come up together at power-up. (This feature has not been tested on the Virtex-4 ML461 Development Board, although there is a provision to do so by populating some 0Ω resistors.) The module output also can be enabled or inhibited through the use of on-board two-pin jumpers (P18, P20, P34, P36, P52, P63).

  • Page 32: Power Connectors

    J8 (RED) for +5V and J7 (BLACK) for GND. The Rev B1 assembly of the Virtex-4 ML461 Development Board does not support the +12V input via jack J5 or via banana jacks J4 and J1 because the power module for the 12V – 5V functionality is not populated.

  • Page 33: Board Design Considerations

    Board Design Considerations Board Design Considerations The Virtex-4 ML461 Development Board design allows for DCI termination to each of the memory interfaces on the board. A preliminary analysis of the Weighted Average Simultaneously Switching Outputs (WASSO) for all four Virtex-4 FPGA devices indicates that the SSO guidelines are met for the current pinout.
  • Page 34 Figure 3-10: ML461 Revision B PCB Stack-up Table 3-15 shows the details of the dielectric material and construction for each layer and the controlled impedance values for the signal layers. www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 35 1.338 <Auto> Dielectric Substrate InnerSignal5 Metal Signal 0.669 <Auto> 51.3 Dielectric Substrate GND5a Metal Solid Plane 1.338 <Auto> Dielectric Substrate InnerSignal6 Metal Signal 0.669 <Auto> 51.3 Dielectric Substrate Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 36 Z0Ω (mils) (mils) GND5 Metal Solid Plane 1.338 <Auto> Dielectric Substrate PWR4 Metal Solid Plane 1.338 <Auto> Dielectric Substrate Bottom Metal Signal 1.338 <Auto> 54.3 Dielectric Solder Mask www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 37: Chapter 4: Electrical Requirements

    40W capacity of the 5V power brick. So an alternate 12V power input jack (J5) is provided on the Virtex-4 ML461 Development Board to hook up a 12V power brick, for example, CUI DTS120500U with a 60W capacity. The 12V is converted to 5V using TI's PTH12010WAS power module (VR6), which can supply up to 12A of current at 5V, or a 60W capacity.
  • Page 38 Termination FCRAM II Memory [S] Toshiba FCRAM-II Data Sheet FCRAM II V Termination RLDRAM II Memory Interface XC4VLX25-FF668: FPGA #4 1.2, 1.8[H], 2921 Virtex-4 Power Estimator (RLDRAM II) www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 39 49.5 12V-to-5V Converter 12000 60.0 TI PTH12010 12A Module Data Sheet Notes: 1. [S] = 1.8V power for SSTL18 plane. 2. [H] = 1.8V power for HSTL18 plane. Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 40 Chapter 4: Electrical Requirements Table 4-2 lists the 12 different power planes on the Virtex-4 ML461 Development Board. Table 4-2: Power Planes Power Power Source +1.2V +1.8V for SSTL18 +1.8V for HSTL18 Texas Instruments PTH05010WAS Modules +2.5V +2.6V +3.3V +0.9V for SSTL18 V +0.9V for SSTL18 V...

  • Page 41: Power Supply 1 5.0 8000

    1500 Micron DDR2 DIMM Data Sheet DDR2 x16 Memory Micron DDR2 Component Data DDR2 x4 Memory Sheet DDR2 x8 Memory FCRAM II Memory [S] Toshiba FCRAM-II Data Sheet Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...

  • Page 42: Ddr1 Dimm Memory

    200-MHz Oscillator Epson EG2121CA Data Sheet 33-MHz Oscillator Epson SG-8002CA Data Sheet 3.3V Power Plane Capacity 15000 49.5 45.6 TI PTH05010 15A Module Datasheet QDR II V Termination www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 43: Ddr1 Dimm Vtt Termination

    12V-to-5V Power Module Capacity 12000 60.0 TI PTH12010 12A Module Data Sheet Notes: 1. [S] = 1.8V power for SSTL18 plane. 2. [H] = 1.8V power for HSTL18 plane. Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...

  • Page 44: Fpga Internal Power Budget

    Bidirectionals Power Measurements on the ML461 This section describes the setup for measuring power on the Virtex-4 ML461 Development Board and lists the power measurements for different designs running on the board. The ML461 board contains four FPGAs that all must be configured for any one design to run on the board.
  • Page 45 0.18 8.87 DDR1 Registered DIMM 1.08 3.00 2.64 1.62 8.06 0.18 16.58 9.93 72-bit Design DDR2 Registered DIMM 2.04 4.50 1.98 9.00 2.86 0.18 20.56 13.91 144-bit Design Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 46 This is evident when comparing the power being consumed at power-up to the power being consumed where all the FPGAs are loaded with a blank design. To learn more about this errata, visit www.xilinx.com. Table 4-7 Table 4-8 show estimated values for current and power consumption not tested on the ML461.
  • Page 47 26.50 19.85 bit Design using SSTL18_II_DCI for DQ and ODT on DDR2 Memory RLDRAM_II 72-bit Design 2.75 1.98 1.98 2.86 2.34 13.59 6.94 (not implemented on the ML461) Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 48 Chapter 4: Electrical Requirements www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 49: Chapter 5: Signal Integrity Recommendations And Simulations

    “IBIS Simulations” Termination and Transmission Line Summaries The following bulleted items provide recommendations for the signal termination scheme to the seven different external memories implemented on the Virtex-4 ML461 Development Board: • Single-ended signals: Simulation indicates that for a single-ended signal, there is no significant performance difference for a signal with split termination of 100Ω...
  • Page 50 Address (A, BA) SSTL2_II No termination 50Ω pull-up to 1.3V after the last component Control (RAS, CAS, WE, SSTL2_II No termination 50Ω pull-up to 1.3V after the last CS, CKE) component www.xilinx.com Virtex-4 ML461 Development Board UG079 (v1.1) September 5, 2007...
  • Page 51 Address (A, BA) HSTL18_I No termination 50Ω pull-up to 0.9V after the last component Control (RAS, CAS, WE, HSTL18_I No termination 50Ω pull-up to 0.9V after the last CS, CKE, BW) component Virtex-4 ML461 Development Board www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 52 IBIS Simulations Signal Integrity (SI) simulations were performed during the Virtex-4 ML461 Development Board layout. The simulations utilized a combination of preliminary Virtex-4 device IBIS and HSPICE models, as well as memory models available from memory vendors at that time.

  • Page 53: Chapter 6: Configuration

    “JTAG Port” • “Parallel Cable IV Port” • “System ACE Interface” Configuration Modes The Virtex-4 ML461 Memory Interfaces Development Board includes several options to configure the Virtex-4 FPGAs. The configuration modes are: • System ACE mode • JTAG mode Table 6-1 shows the Virtex-4 configuration modes.

  • Page 54: Jtag Chain

    Five devices (the System ACE chip and four XC4VLX25-FF668 FPGAs) are connected via a JTAG chain on the Virtex-4 ML461 Development Board. The order of the five devices in the JTAG chain is System ACE chip (U36), FPGA #1 (U15), FPGA #2 (U14), FPGA #3 (U23), and FPGA #4 (U33).

  • Page 55: Parallel Cable Iv Port

    User Defined N/A; goes to PFGA pin V6 Parallel Cable IV Port The Virtex-4 ML461 Development Board provides a Parallel Cable IV connector (P64) to configure the Virtex-4 FPGAs and program JTAG devices located in the JTAG chain. System ACE Interface The Virtex-4 ML461 Development Board provides a System ACE interface to configure the Virtex-4 FPGA.
  • Page 56 Signal Name FPGA Pin Number Pin Number SYSACE_MPD0 AB26 SYSACE_MPD1 AC25 SYSACE_MPD2 SYSACE_MPD3 AA24 SYSACE_MPD4 AC21 SYSACE_MPD5 AB21 SYSACE_MPD6 AB25 SYSACE_MPD7 AB24 SYSACE_CTRL0/MPOE SYSACE_CTRL1/MPWE SYSACE_CTRL2/MPCE SYSACE_CTRL3/MPIRQ SYSACE_CTRL4/MPBRDY SYSACE_CLK AC26 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 57: Appendix A: Fpga Pinouts

    Appendix A FPGA Pinouts This appendix provides the pinouts for the four FPGAs on the Virtex-4 ML461 Development Board. FPGA #1 Pinout Table A-1 lists the connections for FPGA #1 (U14). Table A-1: FPGA #1 Pinout Signal Name Signal Name...
  • Page 58 DDR1_DIMM_DQS_BY1_L_N DDR1_DIMM_DQ_BY0_B3 DDR1_DIMM_DQS_BY1_L_P DDR1_DIMM_DQ_BY0_B4 DDR1_DIMM_DQS_BY2_L_N DDR1_DIMM_DQ_BY0_B5 DDR1_DIMM_DQS_BY2_L_P DDR1_DIMM_DQ_BY0_B6 DDR1_DIMM_DQS_BY3_L_N DDR1_DIMM_DQ_BY0_B7 DDR1_DIMM_DQS_BY3_L_P DDR1_DIMM_DQ_BY1_B0 DDR1_DIMM_DQS_BY4_L_N AC26 DDR1_DIMM_DQ_BY1_B1 DDR1_DIMM_DQS_BY4_L_P AC25 DDR1_DIMM_DQ_BY1_B2 DDR1_DIMM_DQS_BY5_L_N AB21 DDR1_DIMM_DQ_BY1_B3 DDR1_DIMM_DQS_BY5_L_P AC21 DDR1_DIMM_DQ_BY1_B4 DDR1_DIMM_DQS_BY6_L_N DDR1_DIMM_DQ_BY1_B5 DDR1_DIMM_DQS_BY6_L_P DDR1_DIMM_DQ_BY1_B6 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 59 DDR1_DIMM_DQ_BY8_B3 DDR1_DIMM_DQ_BY4_B3 AB24 DDR1_DIMM_DQ_BY8_B4 DDR1_DIMM_DQ_BY4_B3_N DDR1_DIMM_DQ_BY8_B5 DDR1_DIMM_DQ_BY4_B4 AC24 DDR1_DIMM_DQ_BY8_B6 DDR1_DIMM_DQ_BY4_B5 AC23 DDR1_DIMM_DQ_BY8_B7 DDR1_DIMM_DQ_BY4_B6 AD23 DDR1_DIMM_DQ_BY9_B0 DDR1_DIMM_DQ_BY4_B7 AD22 DDR1_DIMM_DQ_BY9_B1 DDR1_DIMM_DQ_BY5_B0 DDR1_DIMM_DQ_BY9_B2 DDR1_DIMM_DQ_BY5_B1 DDR1_DIMM_DQ_BY9_B3 DDR1_DIMM_DQ_BY5_B2 AA19 DDR1_DIMM_DQ_BY9_B4 DDR1_DIMM_DQ_BY5_B3 AA20 DDR1_DIMM_DQ_BY9_B4_N Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 60 DDR1_DIMM_DQ_BY11_B5 DDR1_DIMM_DQ_BY15_B3 DDR1_DIMM_DQ_BY11_B5_N DDR1_DIMM_DQ_BY15_B4 DDR1_DIMM_DQ_BY11_B6 DDR1_DIMM_DQ_BY15_B4_N DDR1_DIMM_DQ_BY11_B7 DDR1_DIMM_DQ_BY15_B5 DDR1_DIMM_DQ_BY12_B0 DDR1_DIMM_DQ_BY15_B6 DDR1_DIMM_DQ_BY12_B0_N DDR1_DIMM_DQ_BY15_B7 DDR1_DIMM_DQ_BY12_B1 DDR1_DIMM_DQ_CB0_7_B0 DDR1_DIMM_DQ_BY12_B1_N DDR1_DIMM_DQ_CB0_7_B0_N DDR1_DIMM_DQ_BY12_B2 DDR1_DIMM_DQ_CB0_7_B1 DDR1_DIMM_DQ_BY12_B2_N DDR1_DIMM_DQ_CB0_7_B1_N DDR1_DIMM_DQ_BY12_B3 DDR1_DIMM_DQ_CB0_7_B2 DDR1_DIMM_DQ_BY12_B4 AA23 DDR1_DIMM_DQ_CB0_7_B3 DDR1_DIMM_DQ_BY12_B5 AB23 DDR1_DIMM_DQ_CB0_7_B4 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 61 AD13 DDR1_DQ_BY0_B1 DDR1_BY0_CS0_N DDR1_DQ_BY0_B2 DDR1_BY0_CS1_N DDR1_DQ_BY0_B3 DDR1_BY1_CS_N DDR1_DQ_BY1_B0 DDR1_BY2_3_CS_N DDR1_DQ_BY1_B1 DDR1_CAS_N AA11 DDR1_DQ_BY1_B2 DDR1_CK0_N AB14 DDR1_DQ_BY1_B3 DDR1_CK0_P AA14 DDR1_DQ_BY1_B4 DDR1_CK1_N AC11 DDR1_DQ_BY1_B5 DDR1_CK1_P AC12 DDR1_DQ_BY1_B6 DDR1_CK2_N AA15 DDR1_DQ_BY1_B7 Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 62 FPGA_CCLK FPGA_PROGB FPGA_CNFG_M0 FPGA_TCK FPGA_CNFG_M1 FPGA_TDO FPGA_CNFG_M2 FPGA_TMS FPGA_DIN FPGA_VBATT FPGA_DONE SYS_RESET_IN_N FPGA_INIT FPGA #1 Test Header Signals FPGA1_TEST_HDR_B0 FPGA1_TEST_HDR_B2 FPGA1_TEST_HDR_B1 FPGA1_TEST_HDR_B3 FPGA #1 Test Header Signals (cont’d) www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 63 FPGA #1 Pinout Table A-1: FPGA #1 Pinout (Continued) Signal Name Signal Name FPGA1_TEST_HDR_B4 FPGA1_TEST_HDR_B6 FPGA1_TEST_HDR_B5 FPGA1_TEST_HDR_B7 Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...

  • Page 64: Fpga #2 Pinout

    DDR2_DIMM_BY0_7_CK2_P DDR2_DIMM_DM_DQS_BY10_H_P DDR2_DIMM_BY0_7_CS_N DDR2_DIMM_DM_DQS_BY11_H_N DDR2_DIMM_BY0_7_ODT DDR2_DIMM_DM_DQS_BY11_H_P DDR2_DIMM_BY8_15_CK0_N DDR2_DIMM_DM_DQS_BY12_H_N DDR2_DIMM_BY8_15_CK0_P DDR2_DIMM_DM_DQS_BY12_H_P DDR2_DIMM_BY8_15_CK1_N DDR2_DIMM_DM_DQS_BY13_H_N DDR2_DIMM_BY8_15_CK1_P DDR2_DIMM_DM_DQS_BY13_H_P DDR2_DIMM_BY8_15_CK2_N DDR2_DIMM_DM_DQS_BY14_H_N AF20 DDR2_DIMM_BY8_15_CK2_P DDR2_DIMM_DM_DQS_BY14_H_P AF19 DDR2_DIMM_BY8_15_CS_N DDR2_DIMM_DM_DQS_BY15_H_N AE18 DDR2_DIMM_BY8_15_ODT DDR2_DIMM_DM_DQS_BY15_H_P AF18 DDR2_DIMM_CAS_N DDR2_DIMM_DM_DQS_CB0_7_H_N www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 65 DDR2_DIMM_DQS_BY11_L_N DDR2_DIMM_DQ_BY2_B1 DDR2_DIMM_DQS_BY11_L_P DDR2_DIMM_DQ_BY2_B2 DDR2_DIMM_DQS_BY12_L_N DDR2_DIMM_DQ_BY2_B3 DDR2_DIMM_DQS_BY12_L_P DDR2_DIMM_DQ_BY2_B4 DDR2_DIMM_DQS_BY13_L_N DDR2_DIMM_DQ_BY2_B5 DDR2_DIMM_DQS_BY13_L_P DDR2_DIMM_DQ_BY2_B6 DDR2_DIMM_DQS_BY14_L_N AC26 DDR2_DIMM_DQ_BY2_B7 DDR2_DIMM_DQS_BY14_L_P AC25 DDR2_DIMM_DQ_BY3_B0 DDR2_DIMM_DQS_BY15_L_N AC19 DDR2_DIMM_DQ_BY3_B1 DDR2_DIMM_DQS_BY15_L_P AD19 DDR2_DIMM_DQ_BY3_B2 DDR2_DIMM_DQS_CB0_7_L_N DDR2_DIMM_DQ_BY3_B3 DDR2_DIMM_DQS_CB0_7_L_P DDR2_DIMM_DQ_BY3_B4 Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 66 DDR2_DIMM_DQ_BY6_B0 DDR2_DIMM_DQ_BY9_B4 DDR2_DIMM_DQ_BY6_B0_N DDR2_DIMM_DQ_BY9_B5 DDR2_DIMM_DQ_BY6_B1 DDR2_DIMM_DQ_BY9_B6 DDR2_DIMM_DQ_BY6_B1_N DDR2_DIMM_DQ_BY9_B7 DDR2_DIMM_DQ_BY6_B2 DDR2_DIMM_DQ_BY10_B0 DDR2_DIMM_DQ_BY6_B2_N DDR2_DIMM_DQ_BY10_B1 DDR2_DIMM_DQ_BY6_B3 DDR2_DIMM_DQ_BY10_B2 DDR2_DIMM_DQ_BY6_B4 AA23 DDR2_DIMM_DQ_BY10_B3 DDR2_DIMM_DQ_BY6_B5 AB23 DDR2_DIMM_DQ_BY10_B4 DDR2_DIMM_DQ_BY6_B6 AD26 DDR2_DIMM_DQ_BY10_B5 DDR2_DIMM_DQ_BY6_B6_N DDR2_DIMM_DQ_BY10_B6 DDR2_DIMM_DQ_BY6_B7 AD25 DDR2_DIMM_DQ_BY10_B7 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 67 AA26 DDR2_DIMM_DQ_CB8_15_B3 DDR2_DIMM_DQ_BY14_B0_N DDR2_DIMM_DQ_CB8_15_B3_N DDR2_DIMM_DQ_BY14_B1 AB26 DDR2_DIMM_DQ_CB8_15_B4 DDR2_DIMM_DQ_BY14_B1_N DDR2_DIMM_DQ_CB8_15_B5 DDR2_DIMM_DQ_BY14_B2 AB25 DDR2_DIMM_DQ_CB8_15_B6 DDR2_DIMM_DQ_BY14_B2_N DDR2_DIMM_DQ_CB8_15_B7 DDR2_DIMM_DQ_BY14_B3 AB24 DDR2_DIMM_RAS_N DDR2_DIMM_DQ_BY14_B3_N DDR2_DIMM_READ_VALID_FAST DDR2_DIMM_DQ_BY14_B4 AC24 DDR2_DIMM_READ_VALID_FAST DDR2_DIMM_DQ_BY14_B5 AC23 DDR2_DIMM_READ_VALID_SLOW DDR2_DIMM_DQ_BY14_B6 AD23 DDR2_DIMM_READ_VALID_SLOW Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 68 DDR2_DQ_BY2_B0 DDR2_CK1_N AC11 DDR2_DQ_BY2_B1 DDR2_CK1_P AC12 DDR2_DQ_BY2_B2 DDR2_CK2_N AA15 DDR2_DQ_BY2_B3 DDR2_CK2_P AA16 DDR2_DQ_BY2_B4 DDR2_CK3_N AD14 DDR2_DQ_BY2_B5 DDR2_CK3_P AC14 DDR2_DQ_BY2_B6 DDR2_CKE AC16 DDR2_DQ_BY2_B7 DDR2_DM_BY0 DDR2_DQ_BY3_B0 DDR2_DM_BY1 DDR2_DQ_BY3_B1 DDR2_DM_BY2 DDR2_DQ_BY3_B2 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 69 FPGA2_FPGA4_MII_TX_SPARE AD11 FPGA4_FPGA2_MII_TX_SPARE AF10 FPGA #2 Configuration Signals FPGA_CNFG_M0 FPGA_PROGB FPGA_CNFG_M1 FPGA_TCK FPGA_CNFG_M2 FPGA_TDO FPGA_DIN FPGA_TMS FPGA_DONE FPGA_VBATT FPGA_INIT SYS_RESET_IN_N FPGA #2 Test Header Signals FPGA2_TEST_HDR_BY0_B0 FPGA2_TEST_HDR_BY0_B2 FPGA2_TEST_HDR_BY0_B1 Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...

  • Page 70: Fpga #3 Pinout

    QDR2_D_BY0_B1 QDR2_D_BY3_B3 AB23 QDR2_D_BY0_B2 QDR2_D_BY3_B4 AA23 QDR2_D_BY0_B3 QDR2_D_BY3_B5 AD22 QDR2_D_BY0_B4 QDR2_D_BY3_B6 AD23 QDR2_D_BY0_B5 QDR2_D_BY3_B7 AC23 QDR2_D_BY0_B6 QDR2_D_BY3_B8 AC24 QDR2_D_BY0_B7 QDR2_D_BY4_B0 QDR2_D_BY0_B8 QDR2_D_BY4_B1 QDR2_D_BY1_B0 QDR2_D_BY4_B2 QDR2_D_BY1_B1 QDR2_D_BY4_B3 QDR2_D_BY1_B2 QDR2_D_BY4_B4 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 71 QDR2_D_BY6_B4 QDR2_Q_BY1_B3 QDR2_D_BY6_B5 QDR2_Q_BY1_B4 QDR2_D_BY6_B6 QDR2_Q_BY1_B5 QDR2_D_BY6_B7 QDR2_Q_BY1_B6 QDR2_D_BY6_B8 QDR2_Q_BY1_B7 QDR2_D_BY7_B0 QDR2_Q_BY1_B8 QDR2_D_BY7_B1 QDR2_Q_BY2_B0 QDR2_D_BY7_B2 QDR2_Q_BY2_B1 QDR2_D_BY7_B3 QDR2_Q_BY2_B2 QDR2_D_BY7_B4 QDR2_Q_BY2_B3 QDR2_D_BY7_B5 QDR2_Q_BY2_B4 QDR2_D_BY7_B6 QDR2_Q_BY2_B5 QDR2_D_BY7_B7 QDR2_Q_BY2_B6 QDR2_D_BY7_B8 QDR2_Q_BY2_B7 Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 72 AB21 QDR2_Q_BY4_B8 QDR2_READ_VALID_LOOPBACK QDR2_Q_BY5_B0 QDR2_READ_VALID_LOOPBACK_BANK7 QDR2_Q_BY5_B1 QDR2_READ_VALID_LOOPBACK_BANK7 QDR2_Q_BY5_B2 QDR2_READ_VALID_LOOPBACK QDR2_Q_BY5_B3 QDR2_READ_VALID_SLOW_LOOPBACK QDR2_Q_BY5_B4 QDR2_READ_VALID_SLOW_LOOPBACK AA20 QDR2_Q_BY5_B5 QDR2_SA0 QDR2_Q_BY5_B6 QDR2_SA1 QDR2_Q_BY5_B7 QDR2_SA2 QDR2_Q_BY5_B8 QDR2_SA3 QDR2_Q_BY6_B0 QDR2_SA4 QDR2_Q_BY6_B1 QDR2_SA5 QDR2_Q_BY6_B2 QDR2_SA6 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 73 FCR2_A10 FCR2_DQ_BY1_B3 FCR2_A11 FCR2_DQ_BY1_B4 FCR2_A12 FCR2_DQ_BY1_B5 FCR2_A13 FCR2_DQ_BY1_B6 FCR2_BA0 FCR2_DQ_BY1_B7 FCR2_BA1 FCR2_DQ_BY1_B8 FCR2_CK0_N FCR2_DQ_BY2_B0 FCR2_CK0_P FCR2_DQ_BY2_B1 FCR2_CK1_N FCR2_DQ_BY2_B2 FCR2_CK1_P FCR2_DQ_BY2_B3 FCR2_CS0_N FCR2_DQ_BY2_B4 FCR2_CS1_N FCR2_DQ_BY2_B5 FCR2_DQ_BY0_B0 FCR2_DQ_BY2_B6 FCR2_DQ_BY0_B1 FCR2_DQ_BY2_B7 Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 74 AE12 FPGA3_FPGA4_MII_TX_EN AE13 FPGA4_FPGA3_MII_TX_ERR AC10 FPGA3_FPGA4_MII_TX_ERR AE10 FPGA4_FPGA3_MII_TX_SPARE AF10 FPGA3_FPGA4_MII_TX_SPARE AD11 FPGA #3 Configuration Signals FPGA_CCLK FPGA_PROGB FPGA_CNFG_M0 FPGA_TCK FPGA_CNFG_M1 FPGA_TDO FPGA_CNFG_M2 FPGA_TMS FPGA_DIN FPGA_VBATT FPGA_DONE SYS_RESET_IN_N FPGA_INIT www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 75 FPGA #3 Test Header Signals FPGA3_TEST_HDR_BY0_B0 FPGA3_TEST_HDR_BY0_B4 FPGA3_TEST_HDR_BY0_B1 FPGA3_TEST_HDR_BY0_B5 FPGA3_TEST_HDR_BY0_B2 FPGA3_TEST_HDR_BY0_B6 FPGA3_TEST_HDR_BY0_B3 FPGA3_TEST_HDR_BY0_B7 Clock Synthesizer Control Signals FPGA1_SYNTH_S_CLK FPGA3_SYNTH_S_CLK FPGA1_SYNTH_S_DATA FPGA3_SYNTH_S_DATA FPGA1_SYNTH_S_LOAD FPGA3_SYNTH_S_LOAD FPGA2_SYNTH_S_CLK FPGA4_SYNTH_S_CLK FPGA2_SYNTH_S_DATA FPGA4_SYNTH_S_DATA CLOCK_SYNTH_MASTER_RESET FPGA4_SYNTH_S_LOAD FPGA2_SYNTH_S_LOAD Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...

  • Page 76: Fpga #4 Pinout

    RLD2_A15 RLD2_QK_BY1_N RLD2_A16 RLD2_QK_BY2_P RLD2_A17 RLD2_QK_BY2_N RLD2_A18 RLD2_QK_BY3_P RLD2_A19 RLD2_QK_BY3_N RLD2_BA0 RLD2_DQ_BY0_B0 RLD2_BA1 RLD2_DQ_BY0_B1 RLD2_BA2 RLD2_DQ_BY0_B2 RLD2_CS_BY0_1_N RLD2_DQ_BY0_B3 RLD2_CS_BY2_3_N RLD2_DQ_BY0_B4 RLD2_DM_BY0_1_N RLD2_DQ_BY0_B5 RLD2_DM_BY2_3_N RLD2_DQ_BY0_B6 RLD2_REF_N RLD2_DQ_BY0_B7 RLD2_QVLD_BY0_1 RLD2_DQ_BY0_B8 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 77 DBG_LED1 CPLD_7 DBG_LED2 CPLD_8 DBG_LED3 CPLD_9 DBG_LED4 CPLD_10 DBG_LED5 CPLD_11 CPLD_0 CPLD_12 CPLD_1 CPLD_13 CPLD_2 CPLD_14 CPLD_3 CPLD_15 CPLD_CLK CPLD_16 CPLD_DGATE_EN CPLD_17 CPLD_GSR LVDS_TX0 CPLD_4 LVDS_TX1 CPLD_5 LVDS_TX2 Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 78 LVDS_TX21 LVDS_RX3 LVDS_TX22 LVDS_RX4 LVDS_TX23 LVDS_RX5 LVDS_TX24 LVDS_RX6 LVDS_TX25 LVDS_RX7 LVDS_TX26 LVDS_RX8 LVDS_TX27 LVDS_RX9 LVDS_TX28 LVDS_RX10 LVDS_TX29 LVDS_RX11 LVDS_TX30 LVDS_RX12 LVDS_TX31 LVDS_RX13 TXPICLKN LVDS_RX14 TXPICLKP LVDS_RX15 TXPCLKP LVDS_RX16 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 79 LVDS_CLKEXT_P LVDS_RX4 LVDS_CLKEXT_N LVDS_RX5 LVDS_CLKEXT_P LVDS_RX6 LVDS_CLKEXT_N LVDS_RX7 SFP0_RXP LVDS_RX8 SFP0_RXN LVDS_RX9 SFP1_RXP LVDS_RX10 SFP1_RXN LVDS_RX11 SFP2_RXP LVDS_RX12 SFP2_RXN AA10 LVDS_RX13 SMA_RXP LVDS_RX14 SMA_RXN LVDS_RX15 XEN_RX0P LVDS_RX16 XEN_RX0N Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 80 FPGA4_FPGA3_MII_TX_CLK AE14 FPGA2_FPGA4_MII_TX_SPARE AD13 FPGA4_FPGA3_MII_TX_DATA0 AD10 FPGA3_FPGA4_MII_TX_CLK AF12 FPGA4_FPGA3_MII_TX_DATA1 AD17 FPGA3_FPGA4_MII_TX_DATA0 AB10 FPGA4_FPGA3_MII_TX_DATA2 AD16 FPGA3_FPGA4_MII_TX_DATA1 AB17 FPGA4_FPGA3_MII_TX_DATA3 AD12 FPGA3_FPGA4_MII_TX_DATA2 AC17 FPGA4_FPGA3_MII_TX_EN AE13 FPGA3_FPGA4_MII_TX_DATA3 AF11 FPGA4_FPGA3_MII_TX_ERR AE10 FPGA3_FPGA4_MII_TX_EN AE12 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 81 SYSACE_MPD6 AB25 SYSACE_MPA3 SYSACE_MPD7 AB24 SYSACE_MPA4 SYSACE_CLK AC26 SYSACE_MPA5 FPGA_DONE AA26 LCD Signals LCD_DB0 AF19 LCD_DB5 AE23 LCD_DB1 AF20 LCD_DB6 LCD_DB2 LCD_DB7 LCD_DB3 LCD_RS AA18 LCD_DB4 AF23 LCD_R_WB Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 82 Voltage Margin Control Signals VMARGIN_UP_VCC1V2_N VMARGIN_DN_3V3_N VMARGIN_DN_VCC1V2_N I2C_CLK VMARGIN_UP_SSTL18_N I2C_DATA VMARGIN_DN_SSTL18_N CPLD_DGATE_EN VMARGIN_UP_SSTL2_N CPLD_GSR VMARGIN_DN_SSTL2_N ENABLE0 VMARGIN_UP_HSTL_N ENABLE1 VMARGIN_DN_HSTL_N ENABLE2 VMARGIN_UP_VCC2V5_N SI_SEL1 VMARGIN_DN_VCC2V5_N MODE” LOOP_FILTER_UP SEL0 LOOP_FILTER_DOWN LOAD VMARGIN_UP_3V3_N SCLK www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 83: Appendix B: Lcd Interface

    This appendix describes the LCD interface for the Virtex-4 ML461 Development Board. General The Virtex-4 ML461 Development Board board has a full graphical LCD display. This display has been chosen because of its possible use in embedded systems. A character-type display also can be connected because the graphical LCD has the same interface as the character-type LCD panels.

  • Page 84: Hardware Schematic Diagram

    ENA, R/W, RSEL, CS1B 3.3V 3.3V IC22 68xx 3.3V IC23 68xx DIP1_4 Default = 68xx Default = Resistor to Gnd Backlight ON/OFF ug079_b_01_081005 Figure B-1: Display Schematic Diagram www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 85: Peripheral Device Ks0713

    Figure B-2: KS0713 Block Diagram Figure B-2 shows only the signals of interest for the LCD controller. Download the data sheet from the Samsung web pages for a complete signal listing. Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 86 LED Backlight 18 LED- ug079_b_03_081005 Figure B-3: 64128EFCBC-XLP Block Diagram 74.00 69.00 56.00 128 x 64 DOTS 2.50 Dimensions in mm 2.54 8.00 Max ug079_b_04_081005 Figure B-4: 64128EFCBC-XLP Dimensions www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 87: Controller - Operation

    ADC control, and LCD outputs (segments). Table B-2: LCD Panel Line DB3 DB2 DB1 DB0 Data Address Page 0 Page 1 Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 88 Appendix B: LCD Interface Table B-2: LCD Panel (Continued) Line DB3 DB2 DB1 DB0 Data Address Page 2 Page 3 Page 4 Page 5 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 89: Controller - Lcd Panel Connections

    The pins in blue connect to default values on the PCB, and the other pins connect to the user-accessible connectors. Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 90 Internal resistors used Normal mode set BSTS Voltage converter input is VDD (2.4<VDD<3.6) OPEN Only used in Master/Slave DISP OPEN Display clock input OPEN Only used in Master/Slave www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 91 LCD driver supply. The relationship of the voltages is V0>V1>V2>V3>V4>VSS. When the internal power supply is active, these voltages are generated. VSS1 DCDC5B Power Supply Control OPEN V0 Adjustment pin Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...

  • Page 92: Controller - Power Supply Circuits

    . INTRS is driven Low when the resistors are external. INTRS is driven High when the resistors are internal. For the Virtex-4 ML461 Development Board, internal resistors are selected. The LCD operating voltage (V0) and the Electronic Volume Voltage (V...

  • Page 93: Operation Example Of The 64128Efcbc-3Lp

    Parallel mode • Internal oscillator • Duty cycle ratio is set to 1/65 • Voltage converter input is between 2.4V ≤ VDD ≤ 3.6V, where VDD connects to 3.3V Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 94 When the RESETB signal is active, ADC is reset to 0, meaning that the segments are scanned from SEG1 up to SEG132. ♦ When ADC is set to 1, the segments are scanned in opposite direction. www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 95 After the display is brought to operational mode, it is best to wait at least 1 ms to ensure the stabilization of power supply levels. After this time, all other necessary display initializations can be performed. Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...

  • Page 96: Instruction Set

    Sets the line address of the display RAM to determine the initial line of the LCD display. Line address 0 Line address 1 Line address 62 Line address 63 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 97 This instruction sets the address of the display data page. Any RAM data bit can be accessed when its page address and column address are specified. Changing the Page Address does not affect the display status. page 0 page 1 page 7 page 8 Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 98 This instruction forces the display to be turned on regardless the contents of the display data RAM. The contents of the display data RAM are saved. This instruction has priority over reverse display. LCD bias select BIAS This instruction selects the LCD bias. Duty Bias = 0 Bias = 1 ratio 1/65 www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 99: Read/Write Characteristics (6800 Mode)

    Address setup time Address hold time Data setup time DB7 to DB0 Data hold time Access time Output disable time System cycle time Enable pulse width Read/write E_RD Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...

  • Page 100: Design Examples

    The interface on the LCD panel side sequentially reads the block RAM, and thus, updates the screen contiguously (like a television screen). The controller (microcontroller or other) side of the block RAM can be written at any time. www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 101: Lcd Panel Used In Character Mode

    When the Enable signal is Low, nothing happens. The display interface design is locked. • When the Enable signal is High and the data_or_command control signal is Low, the byte written is a display command. Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 102 Toplevel.vhd.txt file. Display Data Byte The supplied byte must be a valid ASCII representation of a character as shown in Figure B-9. ug079_b_09_081005 Figure B-9: ASCII Character Representations www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...
  • Page 103 RAM. The result is a stream of bytes representing a character for the display. A small second counter determines when a new character is loaded into the block RAM address counter. Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 104 Timing is met as long as the system clock does not exceed 200 MHz. ® This design can be adapted easily to fit the MicroBlaze™ processor or IBM PowerPC core connect bus system. www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

  • Page 105: Array Connector Numbering

    # NET " " LOC ="AE24 "; #LCD_BL_ON IO_L22N_7 # NET " " LOC ="AE20 "; # LCD_CS1B IO_L23P_VRN_7 # NET " " LOC ="AD20 "; # LCD_RSEL IO_L23N_VRP_7 Virtex-4 ML461 Development Board User Guide www.xilinx.com UG079 (v1.1) September 5, 2007...
  • Page 106 Appendix B: LCD Interface www.xilinx.com Virtex-4 ML461 Development Board User Guide UG079 (v1.1) September 5, 2007...

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