Xilinx Virtex-6 Manual page 90

Chapter 4: About Design Elements
BUFGMUX_CTRL
Primitive: 2-to-1 Global Clock MUX Buffer
Introduction
This design element is a global clock buffer with two clock inputs, one clock output, and a select line used to
cleanly select between one of two clocks driving the global clocking resource. This component is based on
BUFGCTRL, with some pins connected to logic High or Low. This element uses the S pin as the select pin for the
2-to-1 MUX. S can switch anytime without causing a glitch on the output clock of the buffer.
Port Descriptions
Port
O
I0
I1
S0:S1
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
90
Direction
Output
Input
Input
Input
www.xilinx.com
Width
1
1
1
1 each
Yes
Recommended
No
No
Virtex-6 Libraries Guide for HDL Designs
Function
Clock Output
One of two Clock Inputs
One of two Clock Inputs
Clock Select Input. The
S pins represent the clock
select pin for each clock
input. When using the
S pins as input select,
there is a setup/hold time
requirement. Unlike CE
pins, failure to meet this
requirement does not result
in a clock glitch. However, it
can cause the output clock to
appear one clock cycle later.
UG623 (v 14.5) March 20, 2013