Xilinx Virtex-6 Manual page 117

Attribute Data Type Allowed Values Default
USE_MULT String
USE_PATTERN_ String
DETECT
USE_SIMD String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- DSP48E1: 48-bit Multi-Functional Arithmetic Block
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
DSP48E1_inst : DSP48E1
generic map (
-- Feature Control Attributes: Data Path Selection
A_INPUT => "DIRECT",
B_INPUT => "DIRECT",
USE_DPORT => FALSE,
USE_MULT => "MULTIPLY",
-- Pattern Detector Attributes: Pattern Detection Configuration
AUTORESET_PATDET => "NO_RESET",
MASK => X"3fffffffffff",
PATTERN => X"000000000000",
SEL_MASK => "MASK",
SEL_PATTERN => "PATTERN",
USE_PATTERN_DETECT => "NO_PATDET", -- Enable pattern detect ("PATDET" or "NO_PATDET")
-- Register Control Attributes: Pipeline Register Configuration
ACASCREG => 1,
ADREG => 1,
ALUMODEREG => 1,
AREG => 1,
BCASCREG => 1,
BREG => 1,
CARRYINREG => 1,
CARRYINSELREG => 1,
CREG => 1,
DREG => 1,
INMODEREG => 1,
MREG => 1,
OPMODEREG => 1,
PREG => 1,
USE_SIMD => "ONE48"
)
port map (
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
"MULTIPLY", "MULTIPLY"
"DYNAMIC",
"NONE"
"NO_PATDET", "NO_PATDET" Set to PATDET to enable pattern detection in the
"PATDET"
"ONE48", "ONE48"
"FOUR12",
"TWO24"
-- Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
-- Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
-- Select D port usage (TRUE or FALSE)
-- Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
-- "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
-- 48-bit mask value for pattern detect (1=ignore)
-- 48-bit pattern match for pattern detect
-- "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
-- Select pattern value ("PATTERN" or "C")
-- Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
-- Number of pipeline stages for pre-adder (0 or 1)
-- Number of pipeline stages for ALUMODE (0 or 1)
-- Number of pipeline stages for A (0, 1 or 2)
-- Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
-- Number of pipeline stages for B (0, 1 or 2)
-- Number of pipeline stages for CARRYIN (0 or 1)
-- Number of pipeline stages for CARRYINSEL (0 or 1)
-- Number of pipeline stages for C (0 or 1)
-- Number of pipeline stages for D (0 or 1)
-- Number of pipeline stages for INMODE (0 or 1)
-- Number of multiplier pipeline stages (0 or 1)
-- Number of pipeline stages for OPMODE (0 or 1)
-- Number of pipeline stages for P (0 or 1)
-- SIMD selection ("ONE48", "TWO24", "FOUR12")
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Chapter 4: About Design Elements
Description
Selects usage of the Multiplier. Set to NONE to
save power when using only the adder/Logic
Unit. The DYNAMIC setting indicates that
the user is switching between A*B and A:B
operations on the fly and therefore needs to get
the worst case timing of the two paths.
simulation model and speed files.
Selects usage of the SIMD (Single Instruction
Multiple Data) adder/Logic Unit. Selects between
one 48-bit Logic Unit, two 24-bit Logic Units,
or four 12-bit Logic Units. Note that all four
12 bit Logic Units share the same Instruction
(i.e. all can subtract on the same cycle or add
on the same cycle). This allows the 48 bit adder
to be broken up into smaller adders for less
computationally intensive applications. SIMD
only has an effect on arithmetic operation (add,
accumulate, subtract, etc.) and has no effect on
logical operations.
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