Xilinx Virtex-6 Manual page 347

Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
INIT
Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
ROM128X1_inst : ROM128X1
generic map (
INIT => X"00000000000000000000000000000000")
port map (
O => O, -- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3, -- ROM address[3]
A4 => A4, -- ROM address[4]
A5 => A5, -- ROM address[5]
A6 => A6 -- ROM address[6]
);
-- End of ROM128X1_inst instantiation
Verilog Instantiation Template
// ROM128X1: 128 x 1 Asynchronous Distributed (LUT) ROM
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
ROM128X1 #(
.INIT(128'h00000000000000000000000000000000) // Contents of ROM
) ROM128X1_inst (
.O(O), // ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3), // ROM address[3]
.A4(A4), // ROM address[4]
.A5(A5), // ROM address[5]
.A6(A6) // ROM address[6]
);
// End of ROM128X1_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Yes
Recommended
No
No
Allowed Values
Any 128-Bit Value
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Chapter 4: About Design Elements
Default Description
All zeros Specifies the contents of the ROM.
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