Xilinx Virtex-6 Manual page 131

FIFO18E1
Primitive: 18 k-bit FIFO (First In, First Out) Block RAM Memory
Introduction
Virtex®-6 devices contain several block RAM memories, each of which can be separately configured as a FIFO,
an automatic error-correction RAM, or as a general-purpose 36 kb or 18 kb RAM/ROM memory. These Block
RAM memories offer fast and flexible storage of large amounts of on-chip data. The FIFO18E1 uses the FIFO
control logic and the 18 kb block RAM. This primitive can be used in a 4-bit wide by 4K deep, 9-bit wide by 2K
deep, 18-bit wide by 1K deep, or a 36-bit wide by 512 deep configuration. The primitive can be configured in
either synchronous or dual-clock (asynchronous) mode, with all associated FIFO flags and status signals.
When using the dual-clock mode with independent clocks, depending on the offset between read and write clock
edges, the Empty, Almost Empty, Full and Almost Full flags can deassert one cycle later. Due to the asynchronous
nature of the clocks the simulation model only reflects the deassertion latency cycles listed in the User Guide.
Note For a 36-bit wide by 512 deep FIFO, the FIFO18_36 mode must be used. For deeper or wider configurations
of the FIFO, the FIFO36E1 can be used. If error-correction circuitry is desired, the FIFO36E1 with FIFO36_72
mode must be used.
Port Descriptions
Port
ALMOSTEMPTY
ALMOSTFULL
DI[31:0]
DIP[3:0]
DO[31:0]
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width
Output 1
Output 1
Input 32
Input 4
Output 32
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Chapter 4: About Design Elements
Function
Programmable flag to indicate the FIFO is almost
empty. ALMOST_EMPTY_OFFSET attribute specifies
the threshold where this flag is triggered relative to
full/empty.
Programmable flag to indicate that the FIFO is almost
full. The ALMOST_FULL_OFFSET attribute specifies
the threshold where this flag is triggered relative to
full/empty.
FIFO data input bus.
FIFO parity data input bus.
FIFO data output bus.
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