Xilinx Virtex-6 Manual page 135

FIFO36E1
Primitive: 36 kb FIFO (First In, First Out) Block RAM Memory
Introduction
Virtex®-6 devices contain several block RAM memories that can be configured as FIFOs, automatic
error-correction RAM, or general-purpose 36 kb or 18 kb RAM/ROM memories. These block RAM memories
offer fast and flexible storage of large amounts of on-chip data. The FIFO36E1 allows access to the block RAM in
the 36 kb FIFO configurations. This component can be configured and used as a 4-bit wide by 8K deep, 9-bit
by 4K deep, 18-bit by 2K deep, 36-bit wide by 1K deep, or 72-bit wide by 512 deep synchronous or dual-clock
(asynchronous) FIFO RAM with all associated FIFO flags.
When using the dual-clock mode with independent clocks, depending on the offset between read and write clock
edges, the Empty, Almost Empty, Full, and Almost Full flags can deassert one cycle later. Due to the asynchronous
nature of the clocks, the simulation model only reflects the deassertion latency cycles listed in the User Guide.
Note For a 72-bit wide by 512 deep FIFO, the FIFO36_72 mode must be used. For smaller configurations of the
FIFO, the FIFO18E1 can be used. If error-correction circuitry is desired, the FIFO36_72 mode must be used.
Port Descriptions
Port
ALMOSTEMPTY
ALMOSTFULL
DBITERR
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width
Output 1
Output 1
1
Output
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Chapter 4: About Design Elements
Function
Programmable flag to indicate the FIFO is almost
empty. ALMOST_EMPTY_OFFSET attribute specifies
where to trigger this flag.
Programmable flag to indicate the FIFO is almost full.
ALMOST_FULL_OFFSET attribute specifies where to
trigger this flag.
Status output from ECC function to indicate a double
bit error was detected. EN_ECC_READ needs to be
TRUE in order to use this functionality.
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