Xilinx Virtex-6 Manual page 86

Chapter 4: About Design Elements
BUFGMUX
Primitive: Global Clock MUX Buffer
Introduction
BUFGMUX is a multiplexed global clock buffer that can select between two input clocks: I0 and I1. When the
select input (S) is Low, the signal on I0 is selected for output (O). When the select input (S) is High, the signal on
I1 is selected for output.
BUFGMUX and BUFGMUX_1 are distinguished by the state the output assumes when that output switches
between clocks in response to a change in its select input. BUGFMUX assumes output state 0 and BUFGMUX_1
assumes output state 1.
Note BUFGMUX guarantees that when S is toggled, the state of the output remains in the inactive state until the
next active clock edge (either I0 or I1) occurs.
Logic Table
Inputs
I0
I0
X
X
X
Port Descriptions
Port
I0
I1
O
S
Design Entry Method
Instantiation
Inference
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Macro support
86
I1
X
I1
X
X
Direction
Input
Input
Output
Input
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S
0
1
↑
↓
Width
1
1
1
1
Recommended
No
No
No
Virtex-6 Libraries Guide for HDL Designs
Outputs
O
I0
I1
0
0
Function
Clock0 input
Clock1 input
Clock MUX output
Clock select input
UG623 (v 14.5) March 20, 2013