Xilinx Virtex-6 Manual page 42

Chapter 2: About Unimacros
Verilog Instantiation Template
// ADDSUB_MACRO: Variable width & latency - Adder / Subtracter implemented in a DSP48E
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
ADDSUB_MACRO #(
.DEVICE("VIRTEX6"), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
.LATENCY(2), // Desired clock cycle latency, 0-2
.WIDTH(48) // Input / output bus width, 1-48
) ADDSUB_MACRO_inst (
.CARRYOUT(CARRYOUT), // 1-bit carry-out output signal
.RESULT(RESULT),
.A(A),
.ADD_SUB(ADD_SUB),
.B(B),
.CARRYIN(CARRYIN),
.CE(CE),
.CLK(CLK),
.RST(RST)
);
// End of ADDSUB_MACRO_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
42
// Add/sub result output, width defined by WIDTH parameter
// Input A bus, width defined by WIDTH parameter
// 1-bit add/sub input, high selects add, low selects subtract
// Input B bus, width defined by WIDTH parameter
// 1-bit carry-in input
// 1-bit clock enable input
// 1-bit clock input
// 1-bit active high synchronous reset
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013