Xilinx Virtex-6 Manual page 75

Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Data
Attribute Type
JTAG_CHAIN Integer
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BSCAN_VIRTEX6: Boundary Scan
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
BSCAN_VIRTEX6_inst : BSCAN_VIRTEX6
generic map (
DISABLE_JTAG => FALSE, -- This attribute is unsupported. Please leave it at default.
JTAG_CHAIN => 1
)
port map (
CAPTURE => CAPTURE, -- 1-bit output: CAPTURE output from TAP controller
DRCK => DRCK, -- 1-bit output: Data register output for USER functions
RESET => RESET, -- 1-bit output: Reset output for TAP controller
RUNTEST => RUNTEST, -- 1-bit output: State output asserted when TAP controller is in Run Test Idle state.
SEL => SEL, -- 1-bit output: USER active output
SHIFT => SHIFT, -- 1-bit output: SHIFT output from TAP controller
TCK => TCK, -- 1-bit output: Scan Clock output. Fabric connection to TAP Clock pin.
TDI => TDI, -- 1-bit output: TDI output from TAP controller
TMS => TMS, -- 1-bit output: Test Mode Select input. Fabric connection to TAP.
UPDATE => UPDATE, -- 1-bit output: UPDATE output from TAP controller
TDO => TDO -- 1-bit input: Data input for USER function
);
-- End of BSCAN_VIRTEX6_inst instantiation
Verilog Instantiation Template
// BSCAN_VIRTEX6: Boundary Scan
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
BSCAN_VIRTEX6 #(
.DISABLE_JTAG("FALSE"), // This attribute is unsupported. Please leave it at default.
.JTAG_CHAIN(1)
)
BSCAN_VIRTEX6_inst (
.CAPTURE(CAPTURE), // 1-bit output: CAPTURE output from TAP controller
.DRCK(DRCK), // 1-bit output: Data register output for USER functions
.RESET(RESET), // 1-bit output: Reset output for TAP controller
.RUNTEST(RUNTEST), // 1-bit output: State output asserted when TAP controller is in Run Test Idle state.
.SEL(SEL), // 1-bit output: USER active output
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed Values Default
1, 2, 3, 4 1
-- Value for USER command. Possible values: (1,2,3 or 4).
// Value for USER command. Possible values: (1,2,3 or 4).
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Chapter 4: About Design Elements
Recommended
No
No
No
Description
Sets the JTAG USER instruction number that this instance
of the element will handle.
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