Xilinx Virtex-6 Manual page 194

Chapter 4: About Design Elements
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LDPE: Transparent latch with Asynchronous Set and
-- Gate Enable.
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
LDPE_inst : LDPE
generic map (
INIT => '0') -- Initial value of latch ('0' or '1')
port map (
Q => Q, -- Data output
CLR => CLR, -- Asynchronous preset/set input
D => D, -- Data input
G => G, -- Gate input
GE => GE -- Gate enable input
);
-- End of LDPE_inst instantiation
Verilog Instantiation Template
// LDPE: Transparent latch with Asynchronous Preset and Gate Enable.
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
LDPE #(
.INIT(1'b1) // Initial value of latch (1'b0 or 1'b1)
) LDPE_inst (
.Q(Q), // Data output
.PRE(PRE), // Asynchronous preset/set input
.D(D), // Data input
.G(G), // Gate input
.GE(GE) // Gate enable input
);
// End of LDPE_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
194
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013