Xilinx Virtex-6 Manual page 368

Chapter 4: About Design Elements
STARTUP_VIRTEX6
Primitive: Virtex®-6 Configuration Start-Up Sequence Interface
Introduction
This design element is used to interface device pins and logic to the Global Set/Reset (GSR) signal, the Global
Tristate (GTS) dedicated routing, the internal configuration signals, or the input pins for the SPI PROM if
an SPI PROM is used to configure the device. This primitive can also be used to specify a different clock for
the device startup sequence at the End of Configuring of the device, and to access the configuration clock to
the internal logic.
Port Descriptions
Port
CFGCLK
CFGMCLK
CLK
DINSPI
EOS
368
Direction Width
Output 1
Output 1
Input 1
Output 1
Output 1
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Function
Configuration main clock output. This pin is an output
into the FPGA fabric. It outputs a clock signal with the
frequency defined in the Bitgen options. Its source is the
internal ring oscillator.
Configuration internal oscillator clock output. This pin is
an output into the FPGA fabric. It outputs a clock signal
with a constant 50 MHz frequency. Its source is the internal
ring oscillator.
User startup clock. This pin is an input from the FPGA
fabric. It drives the startup clock for the device startup
sequence. It is essentially a user-defined CCLK.
DIN SPI PROM access output. This pin is an output into
the FPGA fabric. The data on this pin is the serial data
being read from a SPI PROM connected to the FPGA. This
pin is useful for reading back SPI PROM contents in order
to perform a "verify" operation.
Active High signal indicates the End Of Configuration.
This pin is an output into the FPGA fabric. It echoes the
"end of startup" flag into the FPGA fabric. This pin can be
used as a reset signal.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013