Xilinx Virtex-6 Manual page 77

BUFG
Primitive: Global Clock Buffer
Introduction
This design element is a high-fanout buffer that connects signals to the global routing resources for low skew
distribution of the signal. BUFGs are typically used on clock nets as well other high fanout nets like sets/resets
and clock enables.
Port Descriptions
Port
I
O
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
BUFG_inst : BUFG
port map (
O => O, -- 1-bit output: Clock buffer output
I => I -- 1-bit input: Clock buffer input
);
-- End of BUFG_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction
Input
Output
www.xilinx.com
Chapter 4: About Design Elements
Width
1
1
Yes
Recommended
No
No
Function
Clock buffer input
Clock buffer output
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