Xilinx Virtex-6 Manual page 50

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Chapter 2: About Unimacros
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute
DEVICE
SEL_PATTERN
MASK
STATIC_PATTERN
SEL_MASK
WIDTH
LATENCY
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- EQ_COMPARE_MACRO: Equality Comparator implemented in a DSP48E
--
Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
EQ_COMPARE_MACRO_inst : EQ_COMPARE_MACRO
generic map (
DEVICE => "VIRTEX6",
LATENCY => 2,
MASK => X"000000000000",
SEL_MASK => "MASK",
SEL_PATTERN => "DYNAMIC_PATTERN", -- "DYNAMIC_PATTERN" = use DYNAMIC_PATTERN input bus
STATIC_PATTERN => X"000000000000", -- Specify static pattern,
WIDTH => 48)
port map (
Q => Q,
-- 1-bit output indicating a match
CE => CE,
-- 1-bit active high input clock enable input
50
Data Type Allowed Values
String
"VIRTEX5",
"VIRTEX6",
"SPARTAN6"
Integer
1 to 24
Hexa-
48 hex
decimal
Hexa-
48 hex
decimal
String
"MASK",
"DYNAMIC_
PATTERN"
Integer
1 to 48
Integer
0, 1, 2, 3
-- Target Device: "VIRTEX5", "VIRTEX6"
-- Desired clock cycle latency, 0-2
-- Select bits to be masked, must set
-- SEL_MASK = "MASK"
-- "MASK" = use MASK generic,
-- "DYNAMIC_PATTERN = use DYNAMIC_PATTERN input bus
-- "STATIC_PATTERN" = use STATIC_PATTERN generic
-- must set SEL_PATTERN = "STATIC_PATTERN
-- Comparator output bus width, 1-48
www.xilinx.com
Yes
No
No
Recommended
Default
Description
"VIRTEX6"
Target hardware architecture.
24
Controls the width of PREADD1
and PREADD2 inputs.
all zeros
Mask to be used for pattern detector.
all zeros
Pattern to be used for pattern
detector.
"MASK"
Selects whether to use the static
MASK or the C input for the mask
of the pattern detector.
48
Width of DATA_IN and
DYNAMIC_PATTERN
2
Number of pipeline registers
1: QREG == 1
2: AREG == BREG == CREG ==
QREG == 1
3: AREG == BREG == 2 and
CREG == QREG == 1
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013

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