Xilinx Virtex-6 Manual page 363

Port Descriptions
Port
Q
D
CLK
CE
A
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
INIT Hexa-
decimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- SRL16E: 16-bit shift register LUT with clock enable operating on posedge of clock
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
SRL16E_inst : SRL16E
generic map (
INIT => X"0000")
port map (
Q => Q, -- SRL data output
A0 => A0, -- Select[0] input
A1 => A1, -- Select[1] input
A2 => A2, -- Select[2] input
A3 => A3, -- Select[3] input
CE => CE, -- Clock enable input
CLK => CLK, -- Clock input
D => D -- SRL data input
);
-- End of SRL16E_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width
Output 1
Input 1
Input 1
Input 1
Input 4
Allowed Values Default
Any 16-Bit Value All zeros
www.xilinx.com
Chapter 4: About Design Elements
Function
Shift register data output
Shift register data input
Clock
Active high clock enable
Dynamic depth selection of the SRL
• A=0000 ==> 1-bit shift length
• A=1111 ==> 16-bit shift length
Yes
Recommended
No
No
Description
Sets the initial value of content and output of shift
register after configuration.
363