Xilinx Virtex-6 Manual page 84

Chapter 4: About Design Elements
Available Attributes
Data
Attribute Type
INIT_OUT Integer
PRESELECT_I0 Boolean
PRESELECT_I1
Boolean
Note Both PRESELECT attributes might not be TRUE at the same time.
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFGCTRL: Global Clock MUX Buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
BUFGCTRL_inst : BUFGCTRL
generic map (
INIT_OUT => 0,
PRESELECT_I0 => FALSE, -- BUFGCTRL output uses I0 input (TRUE/FALSE)
PRESELECT_I1 => FALSE
)
port map (
O => O, -- 1-bit output: Clock Output pin
CE0 => CE0, -- 1-bit input: Clock enable input for I0 input
CE1 => CE1, -- 1-bit input: Clock enable input for I1 input
I0 => I0, -- 1-bit input: Primary clock input
I1 => I1, -- 1-bit input: Secondary clock input
IGNORE0 => IGNORE0, -- 1-bit input: Clock ignore input for I0
IGNORE1 => IGNORE1, -- 1-bit input: Clock ignore input for I1
S0 => S0, -- 1-bit input: Clock select input for I0
S1 => S1 -- 1-bit input: Clock select input for I1
);
-- End of BUFGCTRL_inst instantiation
Verilog Instantiation Template
// BUFGCTRL: Global Clock MUX Buffer
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
BUFGCTRL #(
.INIT_OUT(0),
.PRESELECT_I0("FALSE"), // BUFGCTRL output uses I0 input (TRUE/FALSE)
.PRESELECT_I1("FALSE")
)
BUFGCTRL_inst (
.O(O), // 1-bit output: Clock Output pin
.CE0(CE0), // 1-bit input: Clock enable input for I0 input
.CE1(CE1), // 1-bit input: Clock enable input for I1 input
.I0(I0), // 1-bit input: Primary clock input
.I1(I1), // 1-bit input: Secondary clock input
.IGNORE0(IGNORE0), // 1-bit input: Clock ignore input for I0
.IGNORE1(IGNORE1), // 1-bit input: Clock ignore input for I1
.S0(S0), // 1-bit input: Clock select input for I0
.S1(S1) // 1-bit input: Clock select input for I1
84
Allowed
Values Default
0, 1 0
FALSE, TRUE FALSE
FALSE, TRUE FALSE
-- Initial value of BUFGCTRL output (0/1)
-- BUFGCTRL output uses I1 input (TRUE/FALSE)
// Initial value of BUFGCTRL output (0/1)
// BUFGCTRL output uses I1 input (TRUE/FALSE)
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Description
Initializes the BUFGCTRL output to the specified
value after configuration.
If TRUE, BUFGCTRL output uses I0 input after
configuration.
If TRUE, BUFGCTRL output uses I1 input after
configuration.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013