Xilinx Virtex-6 Manual page 168

Chapter 4: About Design Elements
Port Direction
S Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
• Connect the C pin to the appropriate clock source, representing the positive clock edge and CB to the
clock source representing the negative clock edge.
• Connect the D pin to the top-level input, or bidirectional port, an IODELAY, or an instantiated input
or bidirectional buffer.
• The Q1 and Q2 pins should be connected to the appropriate data sources.
• CE should be tied high when not used, or connected to the appropriate clock enable logic.
• R and S pins should be tied low, if not used, or to the appropriate set or reset generation logic.
• Set all attributes to the component to represent the desired behavior.
• Always instantiate this component in pairs with the same clocking, and to LOC those to the appropriate P
and N I/O pair in order not to sacrifice possible I/O resources.
• Always instantiate this component in the top-level hierarchy of your design, along with any other
instantiated I/O components for the design. This helps facilitate hierarchical design flows/practices.
• To minimize CLK skew, both CLK and CLKB should come from global routing (DCM / MMCM) and not
from the local inversion. DCM / MMCM de-skews these clocks whereas the local inversion adds skew.
Available Attributes
Data
Attribute Type
DDR_CLK_EDGE String
INIT_Q1 Binary
INIT_Q2 Binary
SRTYPE String
168
Width
1
Allowed Values
"OPPOSITE_EDGE",
"SAME_EDGE"
"SAME_EDGE_
PIPELINED"
0, 1
0, 1
"SYNC" or "ASYNC"
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Function
Active high reset forcing Q1 and Q2 to a logic one. Can
be synchronous or asynchronous based on the SRTYPE
attribute.
Recommended
No
No
No
Default Description
"OPPOSITE_ DDR clock mode recovery mode
EDGE" selection. See Introduction for more
explanation.
0 Initial value on the Q1 pin after
configuration startup or when GSR is
asserted.
0 Initial value on the Q2 pin after
configuration startup or when GSR is
asserted.
"SYNC"
Set/reset type selection. "SYNC"
specifies the behavior of the reset (R)
and set (S) pins to be synchronous to
the positive edge of the C clock pin.
"ASYNC" specifies an asynchronous
set/reset function.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013