Xilinx Virtex-6 Manual page 69

Design Element
IBUFG
IBUFGDS
IBUFGDS_DIFF_OUT
IDELAYCTRL
IOBUF
IOBUFDS
IODELAYE1
ISERDESE1
KEEPER
OBUF
OBUFDS
OBUFT
OBUFTDS
OSERDESE1
PULLDOWN
PULLUP
TEMAC_SINGLE
Design Element
FIFO18E1
FIFO36E1
RAM128X1D
RAM256X1S
RAM32M
RAM32X1D
RAM32X1S
RAM32X1S_1
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Description
Primitive: Dedicated Input Clock Buffer
Primitive: Differential Signaling Dedicated Input Clock
Buffer and Optional Delay
Primitive: Differential Signaling Input Buffer with
Differential Output
Primitive: IDELAY Tap Delay Value Control
Primitive: Bi-Directional Buffer
Primitive: 3-State Differential Signaling I/O Buffer with
Active Low Output Enable
Primitive: Input and Output Fixed or Variable Delay
Element
Primitive: Input SERial/DESerializer
Primitive: KEEPER Symbol
Primitive: Output Buffer
Primitive: Differential Signaling Output Buffer
Primitive: 3-State Output Buffer with Active Low Output
Enable
Primitive: 3-State Output Buffer with Differential Signaling,
Active-Low Output Enable
Primitive: Dedicated IOB Output Serializer
Primitive: Resistor to GND for Input Pads, Open-Drain,
and 3-State Outputs
Primitive: Resistor to VCC for Input PADs, Open-Drain,
and 3-State Outputs
Primitive: Tri-mode Ethernet Media Access Controller
(MAC)
RAM/ROM
Description
Primitive: 18 k-bit FIFO (First In, First Out) Block RAM
Memory
Primitive: 36 kb FIFO (First In, First Out) Block RAM
Memory
Primitive: 128-Deep by 1-Wide Dual Port Random Access
Memory (Select RAM)
Primitive: 256-Deep by 1-Wide Random Access Memory
(Select RAM)
Primitive: 32-Deep by 8-bit Wide Multi Port Random
Access Memory (Select RAM)
Primitive: 32-Deep by 1-Wide Static Dual Port Synchronous
RAM
Primitive: 32-Deep by 1-Wide Static Synchronous RAM
Primitive: 32-Deep by 1-Wide Static Synchronous RAM
with Negative-Edge Clock
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Chapter 3: Functional Categories
69