Xilinx Virtex-6 Manual page 257

Attribute
CLKOUT[0:6]_PHASE
CLOCK_HOLD
DIVCLK_DIVIDE
REF_JITTER1
STARTUP_WAIT
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- MMCM_BASE: Base Mixed Mode Clock Manager
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
MMCM_BASE_inst : MMCM_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 5.0,
CLKFBOUT_PHASE => 0.0,
CLKIN1_PERIOD => 0.0,
CLKOUT0_DIVIDE_F => 1.0,
-- CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT6_DUTY_CYCLE => 0.5,
-- CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000).
CLKOUT0_PHASE => 0.0,
CLKOUT1_PHASE => 0.0,
CLKOUT2_PHASE => 0.0,
CLKOUT3_PHASE => 0.0,
CLKOUT4_PHASE => 0.0,
CLKOUT5_PHASE => 0.0,
CLKOUT6_PHASE => 0.0,
-- CLKOUT1_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128)
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Allowed
Data Type Values
3 significant -360.000 to
360.000
digit Float
Boolean FALSE, TRUE
Integer 1 to 128
0.000 to
3 significant
digit Float 0.999
Boolean FALSE
-- Jitter programming ("HIGH","LOW","OPTIMIZED")
-- Multiply value for all CLKOUT (5.0-64.0).
-- Phase offset in degrees of CLKFB (0.00-360.00).
-- Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz).
-- Divide amount for CLKOUT0 (1.000-128.000).
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Chapter 4: About Design Elements
Default Description
0.000 Allows specification of the output phase
relationship of the associated CLKOUT
clock output in number of degrees offset
(for instance, 90 indicates a 90 degree offset
or 1/4 cycle phase offset while 180 indicates
a 180 degree offset or 1/2 cycle phase offset).
FALSE When TRUE, holds the VCO frequency close
to the frequency prior to losing CLKIN.
1 Specifies the division ratio for all output
clocks with respect to the input clock.
Effectively divides the CLKIN going into
the PFD.
0.010
Allows specification of the expected
jitter on the reference clock in order to
better optimize MMCM performance. A
bandwidth setting of OPTIMIZED will
attempt to choose the best parameter for
input clocking when unknown. If known,
then the value provided should be specified
in terms of the UI percentage (the maximum
peak to peak value) of the expected jitter on
the input clock.
FALSE This attribute is not supported.
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