Xilinx Virtex-6 Manual page 196

Chapter 4: About Design Elements
Available Attributes
Attribute Data Type
INIT
Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT1: 1-input Look-Up Table with general output
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
LUT1_inst : LUT1
generic map (
INIT => "00")
port map (
O => O, -- LUT general output
I0 => I0 -- LUT input
);
-- End of LUT1_inst instantiation
Verilog Instantiation Template
// LUT1: 1-input Look-Up Table with general output
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
LUT1 #(
.INIT(2'b00) // Specify LUT Contents
) LUT1_inst (
.O(O), // LUT general output
.I0(I0) // LUT input
);
// End of LUT1_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
196
Allowed Values Default
Any 2-Bit Value All zeros
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Description
Initializes look-up tables.
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013