Xilinx Virtex-6 Manual page 104

Chapter 4: About Design Elements
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- CARRY4: Fast Carry Logic Component
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
CARRY4_inst : CARRY4
port map (
CO => CO, -- 4-bit carry out
O => O, -- 4-bit carry chain XOR data out
CI => CI, -- 1-bit carry cascade input
CYINIT => CYINIT, -- 1-bit carry initialization
DI => DI, -- 4-bit carry-MUX data in
S => S -- 4-bit carry-MUX select input
);
-- End of CARRY4_inst instantiation
Verilog Instantiation Template
// CARRY4: Fast Carry Logic Component
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
CARRY4 CARRY4_inst (
.CO(CO), // 4-bit carry out
.O(O), // 4-bit carry chain XOR data out
.CI(CI), // 1-bit carry cascade input
.CYINIT(CYINIT), // 1-bit carry initialization
.DI(DI), // 4-bit carry-MUX data in
.S(S) // 4-bit carry-MUX select input
);
// End of CARRY4_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
104
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013