Xilinx Virtex-6 Manual page 82

Chapter 4: About Design Elements
-- End of BUFGCE_1_inst instantiation
Verilog Instantiation Template
// BUFGCE_1: Global Clock Buffer with Clock Enable and Output State 1
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
BUFGCE_1 BUFGCE_1_inst (
.O(O), // 1-bit output: Clock buffer output
.CE(CE), // 1-bit input: Clock enable input for I0 input
.I(I) // 1-bit input: Primary clock input
);
// End of BUFGCE_1_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
82
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013