Xilinx Virtex-6 Manual page 334

Chapter 4: About Design Elements
RAMB36E1
Primitive: 36K-bit Configurable Synchronous Block RAM
Introduction
Virtex®-6 devices contain several block RAM memories that can be configured as FIFOs, automatic
error-correction RAM, or general-purpose 36 kb or 18 kb RAM/ROM memories. These Block RAM memories
offer fast and flexible storage of large amounts of on-chip data. This element allows access to the Block RAM
in the 36 kb configurations. This element can be cascaded to create a larger RAM. This component can be
configured and used as a 1-bit wide by 32K deep to a 36-bit wide by 1K deep true dual port RAM. Both read
and write operations are fully synchronous to the supplied clock(s) in the component. However, the READ and
WRITE ports can operate fully independently and asynchronously of each other, accessing the same memory
array. When configured in the wider data width modes, byte-enable write operations are possible, and an
optional output register can be used to reduce the clock-to-out times of the RAM. Error detection and correction
circuitry can also be enabled to uncover and rectify possible memory corruption.
Virtex-6 Libraries Guide for HDL Designs
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