Xilinx Virtex-6 Manual page 121

EFUSE_USR
Primitive: 32-bit non-volatile design ID
Introduction
Provides internal access via JTAG to the 32 non-volatile fuses that can store bits specific to the design (e.g., a
unique ID associated with each design).
Port Descriptions
Port Direction
Output
EFUSEUSR[31:0]
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
SIM_EFUSE_VALUE Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- EFUSE_USR: 32-bit non-volatile design ID
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
EFUSE_USR_inst : EFUSE_USR
generic map (
SIM_EFUSE_VALUE => X"00000000"
)
port map (
EFUSEUSR => EFUSEUSR
);
-- End of EFUSE_USR_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width
32
Allowed Values
32'h00000000 to
32'hffffffff
-- Value of the 32-bit non-volatile design ID used in simulation
-- 32-bit output: User E-Fuse register value output
www.xilinx.com
Chapter 4: About Design Elements
Function
User E-Fuse register value
Recommended
No
No
No
Default Description
32'h00000000 Value of the 32-bit non-volatile design
ID used in simulation.
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