Xilinx Virtex-6 Manual page 278

Chapter 4: About Design Elements
Available Attributes
Data
Attribute Type
DRIVE Integer
IOSTANDARD String
SLEW String
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OBUFT: Single-ended 3-state Output Buffer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
OBUFT_inst : OBUFT
generic map (
DRIVE => 12,
IOSTANDARD => "DEFAULT",
SLEW => "SLOW")
port map (
O => O, -- Buffer output (connect directly to top-level port)
I => I, -- Buffer input
T => T -- 3-state enable input
);
-- End of OBUFT_inst instantiation
Verilog Instantiation Template
// OBUFT: Single-ended 3-state Output Buffer
// All devices
// Xilinx HDL Libraries Guide, version 14.5
OBUFT #(
.DRIVE(12), // Specify the output drive strength
.IOSTANDARD("DEFAULT"), // Specify the output I/O standard
.SLEW("SLOW") // Specify the output slew rate
) OBUFT_inst (
.O(O), // Buffer output (connect directly to top-level port)
.I(I), // Buffer input
.T(T) // 3-state enable input
);
// End of OBUFT_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
278
Allowed Values Default
2, 4, 6, 8, 12, 16, 24 12
See Data Sheet "DEFAULT"
"SLOW" or "FAST" "SLOW"
www.xilinx.com
Description
Specifies the output current drive strength
of the I/O. You should set this to the lowest
setting tolerable for the design drive and
timing requirements.
Assigns an I/O standard to the element.
Specifies the slew rate of the output driver.
See the Data Sheet for recommendations of
the best setting for this attribute.
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013