Xilinx Virtex-5 FPGA ML550 User Manual
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Xilinx Virtex-5 FPGA ML550 User Manual

Xilinx Virtex-5 FPGA ML550 User Manual

Networking interfaces platform
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Virtex-5 FPGA ML550
Networking Interfaces
Platform
User Guide
UG202 (v1.4) April 18, 2008
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Summary of Contents for Xilinx Virtex-5 FPGA ML550

  • Page 1 Virtex-5 FPGA ML550 Networking Interfaces Platform User Guide UG202 (v1.4) April 18, 2008...
  • Page 2 Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 3: Table Of Contents

    LVDS Loopback Board (Xilinx P/N 0431395) ....... . . 29...
  • Page 4 UCF Information ............85 www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 5 ............. 87 ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 6 ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 7: Preface: About This Guide

    This user guide is a description of the Virtex -5 FPGA ML550 Networking Interfaces Development Board. Complete and up-to-date documentation of the Virtex-5 family of FPGAs is available on the Xilinx website at http://www.xilinx.com/virtex5. Guide Contents This manual contains the following chapters: •...

  • Page 8: Additional Support Resources

    PCB and interface level. Additional Support Resources To search the database of silicon and software questions and answers, or to create a technical support case in WebCase, see the Xilinx website at: http://www.xilinx.com/support. www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 9: Typographical Conventions

    Italic font The address (F) is asserted after Emphasis in text clock event 2. Underlined Text Indicates a link to a web page. http://www.xilinx.com/virtex5 Online Document The following conventions are used in this document: Convention Meaning or Use Example See the section “Additional...
  • Page 10 Preface: About This Guide www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 11: Chapter 1: Introduction

    • JTAG cable or Xilinx Platform Cable USB For assistance with any of these items, contact your local Xilinx distributor or visit the Xilinx online store at www.xilinx.com. The heart of the Virtex-5 FPGA ML550 Source-Synchronous Interfaces Tool Kit is the ML550 Development Board.

  • Page 12: Virtex-5 Fpga Ml550 Networking Interfaces Development Board

    Chapter 1: Introduction Virtex-5 FPGA ML550 Networking Interfaces Development Board The ML550 Development Board includes the following: • XC5VLX50T-FFG1136 FPGA • 64M x 8 DDR SDRAM memory • Eight clock sources: ♦ 200 MHz, 250 MHz, 133 MHz, and 33 MHz on-board oscillators ♦...
  • Page 13 PROG Button Power MODE Regulators Switch RESET Button Six User Pushbuttons +5 Volt On/Off and LEDs Power Switch Barrel Jack UG202_c1_01_032607 Figure 1-1: Virtex-5 FPGA ML550 Networking Interfaces Development Board ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 14 Chapter 1: Introduction www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 15: Chapter 2: Getting Started

    Chapter 2 Getting Started This chapter describes the items needed to configure the Virtex-5 FPGA ML550 Networking Interfaces Development Board. The ML550 Development Board is tested at the factory after assembly and should be received in working condition. It is set up to load a bitstream from the CompactFlash card through the System ACE controller U13.

  • Page 16: Installation

    Your new hardware is installed and ready to use. Note: This driver assigns itself the lowest unassigned serial COM port number. This number varies with PC hardware configuration. COM3 or COM4 is typically assigned. www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 17: Bert Gui Tcl Interface Installation

    COM1, COM2, COM3, or COM4, change the port using this path: Control Panel -> System -> Hardware -> Device Manager -> Ports -> CP210x USB to UART-> Port Settings -> Advanced COM Port Number ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 18: Programmable Clock Module Switch Position Chart

    Programmable Clock Module Switch Position Chart Four-Pole SW DIP2 Settings Switch Position Always Eight-Pole SW DIP1 Settings Switch Position 700 MHz 690 MHz 680 MHz 670 MHz 660 MHz 650 MHz 600 MHz 400 MHz www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 19: Chapter 3: Hardware Description

    Chapter 3 Hardware Description A high-level block diagram of the Virtex-5 FPGA ML550 Networking Interfaces Development Board is shown in Figure 3-1, followed by a brief description of each board section. System ACE 64 MByte Module SDRAM Mezzanine Board Connector...

  • Page 20: Clock Generation

    AC30 ICS8442AY to 700 MHz 3.3V LVDS Differential #2 LVDSCLKMOD2B_P and N AK28 AK27 SMA Connector SMA_CLK1_P AF18 SMA Connector SMA_CLK1_N AE18 SMA Connector SMA_CLK2_P AD10 SMA Connector SMA_CLK2_N AD11 www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 21: Sdram Memory

    (FFG1136 Package, Bank 12) Address 0 Address 1 Address 2 Address 3 Address 4 Address 5 Address 6 Address 7 Address 8 Address 9 Address 10 Address 11 Address12 Data 0 Data 1 ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 22: Liquid Crystal Display

    Clock Enable Notes: 1. Because DQS0 is not located on a clock capable I/O pin, the Xilinx MIG tool cannot be used to generate a SDRAM memory controller for the 64M x 8 SDRAM on the ML550 board. Liquid Crystal Display The ML550 Development Board provides an 8-bit interface to a 64 x 128 LCD panel (DisplayTechQ 64128E-FC-BC-3LP, 64 x 128).

  • Page 23: Display Hardware Design

    • External chip select The interface also contains the following built-in options for the display and controller: • On-chip oscillator circuitry • On-chip voltage converter (x2, x3, x4, and x5) ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 24: Hardware Schematic Diagrams

    Backlight − DB[7:0] 3.3V E, R/W, RS, CS1B FPGA 3.3V 3.3V 68xx 8080 Default = 68xx Default = Resistor to GND LCD_BL_ON Backlight ON/OFF ug202_3_03_031106 Figure 3-3: Display Schematic Diagram www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 25: User Led

    The ML550 Development Board provides six user LEDs that can be turned ON by driving the LEDs signal Low. Table 3-5 describes the user LEDs and their associated pin assignments for the FFG1136 FPGA used on the ML550 Development Board. ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 26: Configuration Init And Done Leds

    FPGA Pin Number Signal Switch Designation Description (FFG1136 Package, Bank 18) USER_SW1 USER_SW1 USER_SW2 USER_SW2 USER_SW3 USER_SW3 USER_ SW4 USER_ SW4 USER_SW5 USER_SW5 USER_SW6 USER_SW6 FPGA_RESETB SW10 RESET W34, Bank 13 www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 27: Program Switch

    U2 Pin # Signal Pin # Pin # Signal Name Pin # USB_VBUS USB_DTR_I_B USB_DTR_B USB_D- USB_DSR_I_B USB_DSR_B USB_D+ USB_TX_O USB_TX USB_RX_I USB_RX USB_RTS_O_B USB_RTS_B USB_CTS_I_B USB_CTS_B USB_RESET_I_B USB_RESET_B USB_SUSPEND_O USB_SUSPEND ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 28: Lvds Connectors

    U17 receives the clock waveform from the Samtec LVDS receive connector P6 pins P6.47 and P6.49, on sheet 10. This RCVCLK_P and RCVCLK_N clock waveform drives U17 input pins U17.2 and U17.3 respectively. U17 then www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 29: Lvds Loopback Board (Xilinx P/N 0431395)

    LVDS Loopback Board (Xilinx P/N 0431395) LVDS transmit to receive loopback can be achieved with either the LVDS Loopback board included in the kit, or with the Precision Interconnect Blue Ribbon Cables (Xilinx P/N HW-LVDS-CBL-80, order separately). Appendix B, “LVDS Loopback Board”...
  • Page 30 5. To select other than the nominal output, set up the margin % on VR_SEL[3:0], then strobe the appropriate STB_* from Low to High to Low to clock the value into the latch. www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 31: Important Note About ± 5% Margin Limits

    UG202_3_08_050906 Figure 3-8: Typical Voltage Regulator Configuration Important Note About ± 5% Margin Limits Xilinx devices are specified to work over ±5% power rail variations. In Figure 3-9, the two outer margin resistors in the ±10% and ±7.5% locations are set to the value which gives ±5% regulator output.

  • Page 32: Power Monitor Connector

    Not shown in Figure 3-8 Figure 3-9 is the voltage plane current measurement resistor. Each voltage regulator is routed to its own 10 mΩ 1% 3W Kelvin current sense resistor. The www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 33 DVM reading, apply the negative lead to the S+ pin, and the positive lead to the S– pin. 4. P72 is a 2 x 13 pin header (male) with pins on 0.1-inch centers. ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 34: Ml550 System Monitor And Power Monitor Support

    FPGA pins are used for other functions. Detailed information concerning the System Monitor block is contained in UG192, available at the following link: http://www.xilinx.com/support/documentation/user_guides/ug192.pdf The ML550 system monitor support circuitry is connected to the XC5VLX50T FFG-1136 as shown in Table 3-13.
  • Page 35 30, 34 SM_GPIO3 none 30, 34 SM_GPIO4 none 30, 34 Notes: 1. U15 = MAX4071 current sense amplifier 2. U11 = MAX6608 analog temperature sensor 3. J19 = Hirose expansion connector ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 36: Ml550 Board System Monitor Support Circuitry Details

    Figure 3-12. VCC5_SYSMON_TAP 19,U10.1 R282 R283 9.09K 1.0K VCC5V_MON_SM9P 34,U9.U32 C305 C304 R285 0.1µF R287 0.01µF 1.0K 1.0K 34,U9.U31 VCC5V_MON_SM9N UG202_3_12_041408 Figure 3-12: 5V Input Power Voltage Monitor (Sheet 19) www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 37: Vccaux Voltage Monitor

    Figure 3-14. VCC2V5_VCCO R170 R152 10.0K 1.0K VCCO2V5_MON_SM11P 34,U9.R33 C120 C100 R173 0.001µF 0.01µF R153 4.99K 1.0K 34,U9.R32 VCCO2V5_MON_SM11N R175 10.0K UG202_3_14_041408 Figure 3-14: 2.5V V Voltage Monitor (Sheet 20) ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 38: 2.5V System Power Voltage Monitor

    The signal conditioning network is shown in Figure 3-16. VCC1V0 R281 4.99K 1.0K VCC1V2_MON_SM13P 34,U9.P32 C299 0.001µF 0.01µF 10.0K R280 1.0K 34,U9.N32 VCC1V2_MON_SM13N 4.99K UG202_3_16_041408 Figure 3-16: 1.0V V Voltage Monitor (Sheet 20) CCINT www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 39: Input Power Current Monitor

    19,U10.2 R167 2.49K R278 MAX6608IUK-T 1.0K TEMP_MON_SM15P 34,U9.L34 C107 R158 C287 C103 R275 0.001µF 0.01µF 10.0K 0.1µF 1.0K 34,U9.K34 TEMP_MON_SM15N R155 2.49K UG202_3_18_041508 Figure 3-18: PCB Temperature Monitor (Sheet 19) ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 40: Vref System Monitor

    Table 3-14: System Monitor 2.5V AVDD Reference Options P39 Pins Selected Reference Voltage 1 - 2 U10 TI REF3025 precision 2.5V reference 2 - 3 Filtered 2.5V V FPGA power plane www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 41: J19 Mezzanine Board Connector

    SM_AVDD 30,U9.T18 19,P39.2 VP_SM TD_P VN_SM TD_N VCC5 REF_2V5_OUT 19,U10.2 SM_GPIO1 34,U9.N34 SM_GPIO2 34,U9.P34 SM_GPIO3 SM_GPIO4 34,U9.M32 34,U9.L33 DF9_17S_1V VCC2V5 GNDA UG202_3_20_041508 Figure 3-20: J19 Mezzanine Board Connector (Sheet 30) ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 42 VCC2V5_S– 22,R383.2 22,R383.3 VCC2V5_MON 22,R163.2 VCC3V3_SYS_S+ VCC3V3_SYS_S– 24,R387.3 24,R387.2 VCC3V3_SYS_MON 24,R222.2 19,R131.2 VCC5_MON (5V Current Monitor) VCC5_S+ VCC5_S– 19,R201.2 19,R201.3 HDR_PROTECT 13x2 UG202_3_22_041508 Figure 3-21: P72 Pinout Diagram (Sheet 20) www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 43: Power Monitor Circuitry

    P72 is given in Table 3-12, page Note: As indicated in Note 3 beneath Table 3-12, the S+ and S– pins of P72 are reversed. ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 44: Power Monitor Board

    Table 3-17 shows the manufacturers and part numbers of U10, U11, and U15. Table 3-17: IC Data Sheet References Reference Manufacturer Part Number Designator REF3025AIDBZT Texas Instruments Maxim MAX6608IUK+ Maxim MAX4071AUA+ www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 45: Configuration Modes

    Chapter 4 Configuration The Virtex-5 FPGA ML550 Networking Interfaces Development Board includes several options to configure the Virtex-5 FPGA. The configuration modes are: • System ACE mode • JTAG mode • Slave Serial mode • Master Serial mode This chapter provides a brief description of the FPGA configuration methods used on the ML550 Development Board.

  • Page 46: Jtag Chain

    JTAG chain. The chain can be driven by the following sources: • System ACE controller • Xilinx Parallel Cable IV or Platform Cable USB • Other JTAG cables 2 mm Flat...

  • Page 47: Jtag Ports

    JTAG TCK to System ACE Interface TSTTMS JTAG TMS to System ACE Interface HALTB User Defined N/A; goes to FPGA pin AG5 TRSTB User Defined N/A; goes to FPGA pin AF5 ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 48: Mm Flat Cable Port

    The 2 mm flat cable connector can also be used to configure the FPGA in Slave Serial configuration mode. Parallel Connector 3.3V P51 is a shrouded/keyed connector. 2 mm UG202_4_04_071706 Figure 4-4: 2 mm Flat Cable Connector P51 www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 49: System Ace Interface

    For detailed information on creation of System ACE compatible ACE files, formatting the CF card, and storing multiple design images, see the System ACE CompactFlash Solution Advance Product Specification (DS080) at: http://www.xilinx.com/support/documentation/data_sheets/ds080.pdf ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 50 AC32 SYSACE_MPA4 AD34 SYSACE_MPA5 AC34 SYSACE_MPA6 SYSACE_MPD0 AE32 SYSACE_MPD1 AD32 SYSACE_MPD2 AJ34 SYSACE_MPD3 AH34 SYSACE_MPD4 AE34 SYSACE_MPD5 AF34 SYSACE_MPD6 AE33 SYSACE_MPD7 AF33 SYSACE_CTRL0/MPOE SYSACE_CTRL1/MPWE SYSACE_CTRL2/MPCE AA34 SYSACE_CTRL3/MPIRQ AA33 SYSACE_CTRL4/MPBRDY SYSACE_CLK www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 51: Appendix A: Lvds

    TX Signal Name Pin # Pin # Bank # Pin # Pin # Bank # LVDS_DATAOUT_11N LVDS_DATAOUT_CLKCAP_10N LVDS_DATAOUT_11P LVDS_DATAOUT_CLKCAP_10P LVDS_DATAOUT_CLKCAP_09N AA31 LVDS_DATAOUT_CLKCAP_08N AA30 LVDS_DATAOUT_CLKCAP_09P AB31 LVDS_DATAOUT_CLKCAP_08P AA29 LVDS_DATAOUT_07N AC29 LVDS_DATAOUT_06N AF30 ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 52 LVDS_DATAOUT_18N LVDS_DATAOUT_03N AG31 LVDS_DATAOUT_18P LVDS_DATAOUT_02N AK31 LVDS_DATAOUT_03P AF31 LVDS_DATAOUT_02P AJ31 LVDS_DATAOUT_17N LVDS_DATAOUT_16N LVDS_DATAOUT_17P LVDS_DATAOUT_01N AH30 LVDS_DATAOUT_16P LVDS_DATAOUT_00N AG30 LVDS_DATAOUT_01P AJ30 LVDS_DATAOUT_00P AH29 LVDS_DATAOUT_15N LVDS_DATAOUT_14N LVDS_DATAOUT_15P LVDS_DATAOUT_14P LVDS_DATAOUT_13N LVDS_DATAOUT_12N LVDS_DATAOUT_13P LVDS_DATAOUT_12P www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 53 AH28 LVDS_DATAOUT_26N AE24 LVDS_DATAOUT_25P AG28 LVDS_DATAOUT_26P AD24 LVDS_DATAOUT_23N AF28 LVDS_DATAOUT_24N AF26 LVDS_DATAOUT_23P AE28 LVDS_DATAOUT_24P AF25 GCLK_TX_N AJ27 GCLK_TX_P AK26 LVDS_DATAOUT_21N AG26 LVDS_DATAOUT_22N AA26 LVDS_DATAOUT_21P AG27 LVDS_DATAOUT_22P AA25 LVDS_DATAOUT_35N AA28 XMITCLK_N ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 54 Pin # Bank # Pin # Pin # Bank # LVDS_DATAOUT_45N AM11 LVDS_DATAOUT_46N LVDS_DATAOUT_45P AM12 LVDS_DATAOUT_46P AC10 LVDS_DATAOUT_43N AE11 LVDS_DATAOUT_CLKCAP_44N AJ11 LVDS_DATAOUT_43P AF11 LVDS_DATAOUT_CLKCAP_44P AK11 LVDS_DATAOUT_41N AH10 LVDS_DATAOUT_42N AF10 LVDS_DATAOUT_41P www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 55 LVDS_DATAOUT_39P LVDS_DATAOUT_40P LVDS_DATAOUT_37N LVDS_DATAOUT_38N AG11 LVDS_DATAOUT_37P LVDS_DATAOUT_38P AG10 LVDS_DATAOUT_51N AP14 LVDS_DATAOUT_52N AA10 LVDS_DATAOUT_51P AN14 LVDS_DATAOUT_52P AB10 LVDS_DATAOUT_36N LVDS_DATAOUT_36P LVDS_DATAOUT_49N AM13 LVDS_DATAOUT_50N LVDS_DATAOUT_49P AN13 LVDS_DATAOUT_50P LVDS_DATAOUT_47N AN12 LVDS_DATAOUT_48N LVDS_DATAOUT_47P AP12 LVDS_DATAOUT_48P ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 56: Lvds Receive Connectors

    Pin # Pin # Bank # LVDS_DATAIN_00P LVDS_DATAIN_01P LVDS_DATAIN_00N LVDS_DATAIN_16P LVDS_DATAIN_01N LVDS_DATAIN_17P LVDS_DATAIN_16N LVDS_DATAIN_17N LVDS_DATAIN_02P LVDS_DATAIN_03P LVDS_DATAIN_02N LVDS_DATAIN_18P LVDS_DATAIN_03N LVDS_DATAIN_18N LVDS_DATAIN_04P LVDS_DATAIN_05P LVDS_DATAIN_04N LVDS_DATAIN_05N LVDS_DATAIN_06P LVDS_DATAIN_07P LVDS_DATAIN_06N LVDS_DATAIN_07N LVDS_DATAIN_CLKCAP_08P LVDS_DATAIN_CLKCAP_09P www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 57 RX Signal Name RX Signal Name Pin # Pin # Bank # Pin # Pin # Bank # LVDS_DATAIN_20P LVDS_DATAIN_19P LVDS_DATAIN_20N RCVCLK_P LVDS_DATAIN_19N LVDS_DATAIN_35P RCVCLK_N LVDS_DATAIN_35N LVDS_DATAIN_22P LVDS_DATAIN_21P LVDS_DATAIN_22N LVDS_DATAIN_21N GCLK_RX_P ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 58 Bank # Pin # Pin # Bank # GCLK_RX_N LVDS_DATAIN_24P LVDS_DATAIN_23P LVDS_DATAIN_24N LVDS_DATAIN_23N LVDS_DATAIN_26P LVDS_DATAIN_25P LVDS_DATAIN_26N LVDS_DATAIN_25N LVDS_DATAIN_CLKCAP_28P LVDS_DATAIN_CLKCAP_27P LVDS_DATAIN_CLKCAP_28N LVDS_DATAIN_CLKCAP_27N LVDS_DATAIN_30P LVDS_DATAIN_CLKCAP_29P LVDS_DATAIN_30N LVDS_DATAIN_CLKCAP_29N LVDS_DATAIN_32P LVDS_DATAIN_31P LVDS_DATAIN_32N LVDS_DATAIN_31N LVDS_DATAIN_34P LVDS_DATAIN_33P www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 59 Pin # Bank # Pin # Pin # Bank # LVDS_DATAIN_36P LVDS_DATAIN_36N LVDS_DATAIN_52P LVDS_DATAIN_51P LVDS_DATAIN_52N LVDS_DATAIN_51N LVDS_DATAIN_38P LVDS_DATAIN_37P LVDS_DATAIN_38N LVDS_DATAIN_37N LVDS_DATAIN_40P LVDS_DATAIN_39P LVDS_DATAIN_40N LVDS_DATAIN_39N LVDS_DATAIN_42P LVDS_DATAIN_41P LVDS_DATAIN_42N LVDS_DATAIN_41N LVDS_DATAIN_CLKCAP_44P LVDS_DATAIN_CLKCAP_43P LVDS_DATAIN_CLKCAP_44N ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 60 RX Signal Name RX Signal Name Pin # Pin # Bank # Pin # Pin # Bank # LVDS_DATAIN_CLKCAP_43N LVDS_DATAIN_46P LVDS_DATAIN_45P LVDS_DATAIN_46N LVDS_DATAIN_45N LVDS_DATAIN_48P LVDS_DATAIN_47P LVDS_DATAIN_48N LVDS_DATAIN_47N LVDS_DATAIN_50P LVDS_DATAIN_49P LVDS_DATAIN_50N LVDS_DATAIN_49N www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 61: Appendix B: Lvds Loopback Board

    Appendix B LVDS Loopback Board The Xilinx LVDS Loopback board (P/N 0431395) is an ML550 accessory board that bridges the ML550 LVDS Transmit and Receive Samtec connectors. Figure B-1 is a photograph of the board. UG202_B_01_050906 Figure B-1: Xilinx LVDS Loopback Board The specifications for the loopback board are: •...
  • Page 62 Appendix B: LVDS Loopback Board www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 63: Appendix C: Lcd Interface

    The interface also contains the following built-in options for the display and controller: • On-chip oscillator circuitry • On-chip voltage converter (x2, x3, x4, and x5) • A 64-step electronic contrast control function ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 64: Hardware Schematic Diagram

    IC19 3.3V ENA, R/W, RSEL, CS1B 3.3V 3.3V IC22 68xx 3.3V IC23 68xx DIP1_4 Default = 68xx Default = Resistor to Gnd Backlight ON/OFF UG202_C_01_050906 Figure C-1: Display Schematic Diagram www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 65: Peripheral Device Ks0713

    Circuit Generator Circuit Circuit Column Address Circuit Oscillator Status Register Instruction Register Circuit Bus Holder Instruction Decoder MPU Interface (Parallel and Serial) KS0713 Samsung UG202_C_02_050906 Figure C-2: KS0713 Block Diagram ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 66 17 LED+ LED Backlight 18 LED- UG202_C_03_050906 Figure C-3: 64128EFCBC-XLP Block Diagram 74.00 69.00 56.00 128 x 64 DOTS 2.50 Dimensions in mm 2.54 8.00 Max UG202_C_04_050906 Figure C-4: 64128EFCBC-XLP Dimensions www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 67: Controller - Operation

    Table C-2 shows the input data bytes, address lines, ADC control, and LCD outputs (segments). Table C-2: LCD Panel Line DB3 DB2 DB1 DB0 Data Address Page 0 Page 1 ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 68 Appendix C: LCD Interface Table C-2: LCD Panel (Continued) Line DB3 DB2 DB1 DB0 Data Address Page 2 Page 3 Page 4 Page 5 www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 69 An array of 8x132 bits is available. The line address dictates what line of the RAM is going to be displayed on the first line of the glass panel. ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 70: Controller - Lcd Panel Connections

    DUTY1 Master / Slave operation. Set to Master Built-in oscillator enable TEMPS Set to -0.05%/° C INTRS Internal resistors used Normal mode set BSTS Voltage converter input is VDD (2.4<VDD<3.6) www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 71 LCD driver supply. The relationship of the voltages is V0>V1>V2>V3>V4>VSS. When the internal power supply is active, these voltages are generated. VSS1 DCDC5B Power Supply Control OPEN V0 Adjustment pin ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 72: Controller - Power Supply Circuits

    LCD controller’s instruction registers. Thus, it is possible to change physical operating parameters of the LCD through register bit settings, controlling the operating voltage, and the electronic volume level. www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 73: Operation Example Of The 64128Efcbc-3Lp

    Duty cycle ratio is set to 1/65 • Voltage converter input is between 2.4V ≤ VDD ≤ 3.6V, where VDD connects to 3.3V • Internal voltage divider resistors • Temperature coefficient is set to -0.05%/° C ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 74 Configure the SHL bit. This bit sets the scanning direction of the COM lines. ♦ When the RESETB signal is active, SHL is reset to 0, meaning that the segments are scanned from COM1 up to COM64. www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 75 After the display is brought to operational mode, it is best to wait at least 1 ms to ensure the stabilization of power supply levels. After this time, all other necessary display initializations can be performed. ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 76: Instruction Set

    Line address 63 Set reference voltage mode Set reference voltage register This is a two-byte instruction. The first instruction sets the reference voltage mode. The second instruction sets the reference voltage parameter. www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 77 Addr Addr ADC select This instruction changes the relationship between RAM column address and segment driver. ADC = 0, SEG1 --> SEG132 default mode ADC = 1, SEG132 --> SEG1 ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 78 Set static indicator mode Set static indicator register This is a two-byte instruction. The first instruction enables the second instruction. The second instruction update the contents of the static indicator register. www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 79: Read/Write Characteristics (6800 Mode)

    T AS T AH CS1B T CYC T PWR T PWW T DS T DH WRITE DB0-DB7 T ACC T OD READ UG202_C_07_050906 Figure C-7: Read/Write Timing Waveforms (6800 Mode) ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...

  • Page 80: Design Examples

    Most of the time LCD panels operate in write-only mode. At first the block RAM must be initialized with some data (instructions to the LCD) to make the LCD operate correctly. www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 81: Lcd Panel Used In Character Mode

    When this initialization is done, the normal LCD display interface is freed for normal use. Command bytes from the valid command set can be sent to the display (controller). A detailed description of the LCD controller interface can be found in the Toplevel.vhd.txt file. ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 82 The character set is stored in block RAM (used as ROM). For the layout of the block RAM character set, see the CharacterSet.xls file. The block RAM (see Figure C-10) is organized as small arrays of eight bytes, which is easy for address calculation. www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 83 RAM. The result is a stream of bytes representing a character for the display. A small second counter determines when a new character is loaded into the block RAM address counter. ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 84 Timing is met as long as the system clock does not exceed 200 MHz. This design can be adapted easily to fit the MicroBlaze™ or PPC405 CoreConnect bus system. www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...

  • Page 85: Array Connector Numbering

    # NET " " LOC ="H21 "; # LCD_RSEL IO0L09N # NET " " LOC ="G21 "; # LCD_RW IO0L09P # NET " " LOC ="H22 "; # LCD_ENA IO0L06N ML550 Networking Interfaces Platform www.xilinx.com UG202 (v1.4) April 18, 2008...
  • Page 86 Appendix C: LCD Interface www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 87 Appendix D ML550 Starter UCF UCF Starter File The ML550 UCF starter file (ml550_starter.ucf) can be downloaded from the Xilinx website at: https://secure.xilinx.com/webreg/clickthrough.do?cid=37487. Complete FPGA pinout information is included on the CD shipped with the Virtex-5 FPGA ML550 Networking Interfaces Platform kit.
  • Page 88 Appendix D: ML550 Starter UCF www.xilinx.com ML550 Networking Interfaces Platform UG202 (v1.4) April 18, 2008...
  • Page 89 This datasheet has been downloaded from: datasheet.eeworld.com.cn Free Download Daily Updated Database 100% Free Datasheet Search Site 100% Free IC Replacement Search Site Convenient Electronic Dictionary Fast Search System www.EEworld.com.cn All Datasheets Cannot Be Modified Without Permission Copyright © Each Manufacturing Company...

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