Xilinx Virtex-6 Manual page 171

VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- IDELAYCTRL : Input Delay Element Control
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
IDELAYCTRL_inst : IDELAYCTRL
port map (
RDY => RDY, -- 1-bit output indicates validity of the REFCLK
REFCLK => REFCLK, -- 1-bit reference clock input
RST => RST -- 1-bit reset input
);
-- End of IDELAYCTRL_inst instantiation
Verilog Instantiation Template
// IDELAYCTRL: IDELAY Tap Delay Value Control
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
(* IODELAY_GROUP = "<iodelay_group_name>" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
IDELAYCTRL IDELAYCTRL_inst (
.RDY(RDY), // 1-bit Ready output
.REFCLK(REFCLK), // 1-bit Reference clock input
.RST(RST) // 1-bit Reset input
);
// End of IDELAYCTRL_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Sheets).
www.xilinx.com
Chapter 4: About Design Elements
171