Xilinx Virtex-6 Manual page 179

CLKIN => CLKIN,
CNTVALUEIN => CNTVALUEIN,
DATAIN => DATAIN,
IDATAIN => IDATAIN,
INC => INC,
ODATAIN => ODATAIN,
RST => RST,
T => T
);
-- End of IODELAYE1_inst instantiation
Verilog Instantiation Template
// IODELAYE1: Input / Output Fixed or Variable Delay Element
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
(* IODELAY_GROUP = "<iodelay_group_name>" *) // Specifies group name for associated IODELAYs and IDELAYCTRL
IODELAYE1 #(
.CINVCTRL_SEL("FALSE"),
.DELAY_SRC("I"),
.HIGH_PERFORMANCE_MODE("FALSE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
.IDELAY_TYPE("DEFAULT"),
.IDELAY_VALUE(0),
.ODELAY_TYPE("FIXED"),
.ODELAY_VALUE(0),
.REFCLK_FREQUENCY(200.0),
.SIGNAL_PATTERN("DATA")
)
IODELAYE1_inst (
.CNTVALUEOUT(CNTVALUEOUT), // 5-bit output - Counter value for monitoring purpose
.DATAOUT(DATAOUT),
.C(C),
.CE(CE),
.CINVCTRL(CINVCTRL),
.CLKIN(CLKIN),
.CNTVALUEIN(CNTVALUEIN),
.DATAIN(DATAIN),
.IDATAIN(IDATAIN),
.INC(INC),
.ODATAIN(ODATAIN),
.RST(RST),
.T(T)
);
// End of IODELAYE1_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
-- 1-bit input - Clock Access into the IODELAY
-- 5-bit input - Counter value for loadable counter application
-- 1-bit input - Internal delay data
-- 1-bit input - Delay data input
-- 1-bit input - Increment / Decrement tap delay
-- 1-bit input - Data input for the output datapath from the device
-- 1-bit input - Active high, synchronous reset, resets delay chain to IDELAY_VALUE/
-- ODELAY_VALUE tap. If no value is specified, the default is 0.
-- 1-bit input - 3-state input control. Tie high for input-only or internal delay or
-- tie low for output only.
// Enable dynamic clock inversion ("TRUE"/"FALSE")
// Delay input ("I", "CLKIN", "DATAIN", "IO", "O")
// "DEFAULT", "FIXED", "VARIABLE", or "VAR_LOADABLE"
// Input delay tap setting (0-32)
// "FIXED", "VARIABLE", or "VAR_LOADABLE"
// Output delay tap setting (0-32)
// IDELAYCTRL clock input frequency in MHz
// "DATA" or "CLOCK" input signal
// 1-bit output - Delayed data output
// 1-bit input - Clock input
// 1-bit input - Active high enable increment/decrement function
// 1-bit input - Dynamically inverts the Clock (C) polarity
// 1-bit input - Clock Access into the IODELAY
// 5-bit input - Counter value for loadable counter application
// 1-bit input - Internal delay data
// 1-bit input - Delay data input
// 1-bit input - Increment / Decrement tap delay
// 1-bit input - Data input for the output datapath from the device
// 1-bit input - Active high, synchronous reset, resets delay chain to IDELAY_VALUE/
// ODELAY_VALUE tap. If no value is specified, the default is 0.
// 1-bit input - 3-state input control. Tie high for input-only or internal delay or
// tie low for output only.
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