Xilinx Virtex-6 Manual page 355

Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
INIT
Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
ROM64X1_inst : ROM64X1
generic map (
INIT => X"0000000000000000")
port map (
O => O, -- ROM output
A0 => A0, -- ROM address[0]
A1 => A1, -- ROM address[1]
A2 => A2, -- ROM address[2]
A3 => A3, -- ROM address[3]
A4 => A4, -- ROM address[4]
A5 => A5 -- ROM address[5]
);
-- End of ROM64X1_inst instantiation
Verilog Instantiation Template
// ROM64X1: 64 x 1 Asynchronous Distributed (LUT) ROM
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
ROM64X1 #(
.INIT(64'h0000000000000000) // Contents of ROM
) ROM64X1_inst (
.O(O), // ROM output
.A0(A0), // ROM address[0]
.A1(A1), // ROM address[1]
.A2(A2), // ROM address[2]
.A3(A3), // ROM address[3]
.A4(A4), // ROM address[4]
.A5(A5) // ROM address[5]
);
// End of ROM64X1_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Yes
Recommended
No
No
Allowed Values Default
Any 64-Bit Value All zeros
www.xilinx.com
Chapter 4: About Design Elements
Description
Specifies the contents of the ROM.
Sheets).
355