Xilinx Virtex-6 Manual page 224

Chapter 4: About Design Elements
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
INIT
Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT5: 5-input Look-Up Table with general output
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
LUT5_inst : LUT5
generic map (
INIT => X"00000000") -- Specify LUT Contents
port map (
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2, -- LUT input
I3 => I3, -- LUT input
I4 => I4 -- LUT input
);
-- End of LUT5_inst instantiation
Verilog Instantiation Template
// LUT5: 5-input Look-Up Table with general output
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
LUT5 #(
.INIT(32'h00000000)
) LUT5_inst (
.O(O), // LUT general output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2), // LUT input
.I3(I3), // LUT input
.I4(I4) // LUT input
);
// End of LUT5_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
224
Allowed
Values
Any 32-Bit Value
// Specify LUT Contents
www.xilinx.com
Yes
Recommended
No
No
Default Description
All zeros Specifies the logic value for the look-up
tables.
Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013