Xilinx Virtex-6 Manual page 115

Port
PCIN[47:0]
PCOUT[47:0]
RSTA
RSTALLCARRYIN
RSTALUMODE
RSTB
RSTC
RSTCTRL
RSTD
RSTINMODE
RSTM
RSTP
UNDERFLOW
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type Allowed Values Default
A_INPUT String
ACASCREG Integer
Integer
ADREG
ALUMODEREG Integer
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width Function
Input 48 Cascade input for Port P. If used, connect to PCOUT of upstream
cascaded DSP slice. If not used, tie port to all zeros.
Output 48
Cascade output for Port P. If used, connect to PCIN of downstream
cascaded DSP slice. If not used, leave unconnected.
Input 1 Active High, synchronous reset for the A port registers (AREG=1 or
2). Tie to logic zero if not used.
Input 1
Active High, synchronous reset for all carry-in registers
(CARRYINREG=1). Tie to logic zero if not used.
Input 1
Active High, synchronous reset for the ALUMODE registers
(ALUMODEREG=1). Tie to logic zero if not used.
Input 1 Active High, synchronous reset for the B port registers (BREG=1 or
2). Tie to logic zero if not used.
Input 1
Active High, synchronous reset for the C port registers (CREG=1).
Tie to logic zero if not used.
Input 1 Active High, synchronous reset for the OPMODE and CARRYINSEL
registers (OPMODEREG=1 and CARRYINSELREG=1). Tie to logic
zero if not used.
Input 1
Active High, synchronous reset for the D port registers (DREG=1).
Tie to logic zero if not used.
Input 1 Active High, synchronous reset for the INMODE registers
(INMODEREG=1). Tie to logic zero if not used.
Input 1
Active High, synchronous reset for the multiplier registers
(MREG=1). Tie to logic zero if not used.
Input 1
Active High, synchronous reset for the output registers (PREG=1).
Tie to logic zero if not used.
Output 1 Active High output detects underflow in addition/accumulate if
pattern detector is used and PREG = 1.
"DIRECT", "DIRECT"
"CASCADE"
1, 0, 2 1
1, 0 1
1, 0 1
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Chapter 4: About Design Elements
Yes
Recommended
No
Yes
Description
Selects between A and ACIN inputs.
In conjunction with AREG, selects the number of
A input registers on A cascade ACOUT. Must be
equal to or one less than AREG value.
Selects usage of Pre-adder output (AD) Pipeline
Registers. Set to 1 to use the AD Pipeline
Registers.
Set to 1 to register the ALUMODE inputs.
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