Xilinx Virtex-6 Manual page 101

CAPTURE_VIRTEX6
Primitive: Virtex®-6 Readback Register Capture Control
Introduction
This element provides user control and synchronization over when and how the capture register (flip-flop and
latch) information task is requested. The readback function is provided through dedicated configuration port
instructions. However, without this element, the readback data is synchronized to the configuration clock.
Only register (flip-flop and latch) states can be captured. Although LUT RAM, SRL, and block RAM states
are readback, they cannot be captured.
An asserted high CAP signal indicates that the registers in the device are to be captured at the next Low-to-High
clock transition. By default, data is captured after every trigger when transition on CLK while CAP is asserted.
To limit the readback operation to a single data capture, add the ONESHOT=TRUE attribute to this element.
Port Descriptions
Port Direction
CAP Input
CLK Input
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Connect all inputs and outputs to the design in order to ensure proper operation.
Available Attributes
Data
Attribute Type
ONESHOT Boolean
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width
1
1
Allowed
Values Default
TRUE, FALSE TRUE
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Chapter 4: About Design Elements
Function
Readback capture trigger
Readback capture clock
Recommended
No
No
No
Description
Specifies the procedure for performing single readback per
CAP trigger.
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