Xilinx Virtex-6 Manual page 204

Chapter 4: About Design Elements
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT2_D: 2-input Look-Up Table with general and local outputs
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
LUT2_D_inst : LUT2_D
generic map (
INIT => X"0")
port map (
LO => LO, -- LUT local output
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1 -- LUT input
);
-- End of LUT2_D_inst instantiation
Verilog Instantiation Template
// LUT2_D: 2-input Look-Up Table with general and local outputs
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
LUT2_D #(
.INIT(4'h0) // Specify LUT Contents
) LUT2_D_inst (
.LO(LO), // LUT local output
.O(O), // LUT general output
.I0(I0), // LUT input
.I1(I1) // LUT input
);
// End of LUT2_L_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
204
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013