Xilinx Virtex-6 Manual page 95

);
-- End of BUFHCE_inst instantiation
Verilog Instantiation Template
// BUFHCE: HROW Clock Buffer for a Single Clocking Region with Clock Enable
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
BUFHCE #(
.INIT_OUT(0) // Initial output value
)
BUFHCE_inst (
.O(O), // 1-bit output: Clock output
.CE(CE), // 1-bit input: Active high enable input
.I(I) // 1-bit input: Clock input
);
// End of BUFHCE_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Sheets).
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Chapter 4: About Design Elements
95