Xilinx Virtex-6 Manual page 122

Chapter 4: About Design Elements
Verilog Instantiation Template
// EFUSE_USR: 32-bit non-volatile design ID
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
EFUSE_USR #(
.SIM_EFUSE_VALUE(32'h00000000)
)
EFUSE_USR_inst (
.EFUSEUSR(EFUSEUSR)
);
// End of EFUSE_USR_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
122
// Value of the 32-bit non-volatile design ID used in simulation
// 32-bit output: User E-Fuse register value output
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013