Table Of Contents - Xilinx Virtex-6 Manual

Inputs
I3 I2
1 1
1 1
INIT = Binary equivalent of the hexadecimal number assigned to the INIT attribute
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute Data Type
INIT Hexadecimal
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- LUT4_D: 4-input Look-Up Table with general and local outputs
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
LUT4_D_inst : LUT4_D
generic map (
INIT => X"0000")
port map (
LO => LO, -- LUT local output
O => O, -- LUT general output
I0 => I0, -- LUT input
I1 => I1, -- LUT input
I2 => I2, -- LUT input
I3 => I3 -- LUT input
);
-- End of LUT4_D_inst instantiation
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
I1 I0
1 0
1 1
Allowed Values
Any 16-Bit Value
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Chapter 4: About Design Elements
Outputs
O
INIT[14]
INIT[15]
Yes
Recommended
No
No
Default Description
All zeros Initializes look-up tables.
LO
INIT[14]
INIT[15]
217