Xilinx Virtex-6 Manual page 379

Chapter 4: About Design Elements
Design Entry Method
To instantiate this component, use the Embedded Development Kit (EDK) or an associated core containing the
component. Xilinx does not recommend direct instantiation of this component.
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data Sheets).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013 www.xilinx.com 379