Xilinx Virtex-6 Manual page 335

Port Descriptions
Port
ADDRARDADDR[15:0]
ADDRBWRADDR[15:0]
CASCADEINA
CASCADEINB
CASCADEOUTA
CASCADEOUTB
CLKARDCLK
CLKBWRCLK
DBITERR
DIADI[31:0]
DIBDI[31:0]
DIPADIP[3:0]
DIPBDIP[3:0]
DOADO[31:0]
DOBDO[31:0]
DOPADOP[3:0]
DOPBDOP[3:0]
ECCPARITY[7:0]
ENARDEN
ENBWREN
INJECTDBITERR
INJECTSBITERR
RDADDRECC[8:0]
REGCEAREGCE
REGCEB
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width Function
Input 16
Port A address input bus/Read address input bus.
Input 16
Port B address input bus/Write address input bus.
Input 1
Port A cascade input. Never use when RAM_MODE=SDP.
Input 1
Port B cascade input. Never use when RAM_MODE=SDP.
1
Output Port A cascade output. Never use when RAM_MODE=SDP.
1
Output Port B cascade output. Never use when RAM_MODE=SDP.
Input 1
Port A clock input/Read clock input.
Input 1 Port B clock input/Write clock input.
Output 1 Status output from ECC function to indicate a double bit error was
detected. Set EN_ECC_READ to TRUE to use this functionality.
Not used when RAM_MODE=TDP.
Input 32
Port A data input bus/Data input bus addressed by WRADDR.
When RAM_MODE=SDP, DIADI is the logical DI[31:0].
Input 32 Port B data input bus/Data input bus addressed by WRADDR.
When RAM_MODE=SDP, DIBDI is the logical DI[63:32].
Input 4 Port A parity data input bus/Data parity input bus addressed
by WRADDR. When RAM_MODE=SDP, DIPADIP is the logical
DIP[3:0].
Input 4
Port B parity data input bus/Data parity input bus addressed
by WRADDR. When RAM_MODE=SDP, DIPBDIP is the logical
DIP[7:4].
32
Output Port A data output bus/Data output bus addressed by RDADDR.
When RAM_MODE=SDP, DOADO is the logical DO[31:0].
Output 32
Port B data output bus/Data output bus addressed by RDADDR.
When RAM_MODE=SDP, DOBDO is the logical DO[63:32].
Output 4 Port A parity data output bus/Data parity output bus addressed
by RDADDR. When RAM_MODE=SDP, DOPADOP is the logical
DOP[3:0].
Output 4
Port B parity data output bus/Data parity output bus addressed
by RDADDR. When RAM_MODE=SDP, DOPBDOP is the logical
DOP[7:4].
Output 8 8-bit data generated by the ECC encoder used by the ECC
decoder for memory error detection and correction. Not used if
RAM_MODE=TDP.
Input 1
Port A RAM enable/Read enable.
Input 1
Port B RAM enable/Write enable.
Input 1
Inject a double bit error if ECC feature is used.
Input 1
Inject a single bit error if ECC feature is used.
Output 9
9-bit ECC read address. Not used when RAM_MODE=TDP.
Input 1
Port A output register clock enable input/Output register clock
enable input (valid only when DO_REG=1).
Input 1 Port B output register clock enable (valid only when DO_REG=1
and RAM_MODE=TDP).
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Chapter 4: About Design Elements
335