Xilinx Virtex-6 Manual page 161

ICAP_VIRTEX6
Primitive: Internal Configuration Access Port
Introduction
This design element gives you access to the configuration functions of the FPGA from the FPGA fabric. Using
this component, commands and data can be written to and read from the configuration logic of the FPGA array.
Since the improper use of this function can have a negative effect on the functionality and reliability of the FPGA,
you should not use this element unless you are very familiar with its capabilities.
Port Descriptions
Port
BUSY
CLK
CSB
I[31:0]
O[31:0]
RDWRB
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Direction Width Function
Output 1
Busy/Ready output.
Input 1
Clock Input.
Input 1
Active-Low ICAP Enable.
Input 32
Configuration data input bus.
Output 32
Configuration data output bus.
Input 1
Read/Write Select.
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Chapter 4: About Design Elements
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