Xilinx Virtex-6 Manual page 215

Verilog Instantiation Template
// LUT4: 4-input Look-Up Table with general output
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
LUT4 #(
.INIT(16'h0000) // Specify LUT Contents
) LUT4_inst (
.O(O), // LUT general output
.I0(I0), // LUT input
.I1(I1), // LUT input
.I2(I2), // LUT input
.I3(I3) // LUT input
);
// End of LUT4_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Sheets).
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Chapter 4: About Design Elements
215