Xilinx VIRTEX-6 Hardware Setup Manual

HARDwARE SETUP GUIDE
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Performance Monitor Application: Start Data Traffic
A. Click on Start Test to begin XAUI data transfer.
B. Click on Start Test to begin Raw data transfer.
Congratulations! The Virtex-6 FPGA Connectivity Kit is now set up. The pre-built connectivity targeted reference design demonstration has
been tested, using the built-in block for PCI Express (x4 PCI Express Gen2 Endpoint), XAUI LogiCORE IP, a Virtual FIFO memory controller
designed to interface to the on-board DDR3 memory, and Northwest Logic's high performance DMA controller for PCI Express.
Next, please refer the Getting Started Guide included in this kit. The guide provides further instructions on running the demo, evaluating and
modifying the design files – Hardware RTL design and Software Device Driver. For updated information on this Virtex-6 FPGA Connectivity
Kit, please visit www.xilinx.com/v6connkit.
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VIRTEX-6 FPGA CONNECTIVITY KIT
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Performance Monitor Application: Verify Data Throughput
and Error Free Operation
A. Confirm PCIe Throughput.
B. Confirm DMA Channel throughput for the XAUI path.
C. Confirm DMA Channel throughput for the Raw Data path.
D. Confirm Error Free operation - no Buffer Descriptor Errors.
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Xilinx K.K. Xilinx, Asia Pacific
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Tower 4F Singapore 486040
1-2-2 Osaki, Shinagawa-ku Tel: +65-6407-3000
Tokyo 141-0032 Japan www.xilinx.com
Tel: +81-3-6744-7777
japan.xilinx.com
Xilinx Part Number: PN0402827-01
HARDwARE SETUP GUIDE
VIRTEX-6 FPGA CONNECTIVITY KIT HARDwARE SETUP GUIDE
This Hardware Setup Guide provides step-by-step instructions to setup the ML605 board, the FMC daughter card, and run the pre-built
Demo that uses the built-in block for PCI Express (x4Gen2 configuration), XAUI IP LogiCORE, a Virtual FIFO Memory controller interfacing
to the on-board DDR3 memory and a third-party PCIe DMA Controller.
B OAR D F EATU R ESXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
GPIO LEDs CX4 Connector
Clock Generator
and Synthesizer
GPIO DIP Switch (SW1)
FMC User Clock
SFP DDR3 (LPC) (J55-J58)
MGT Clock (J30 & J31)
USB to UART (J21)
USB JTAG (J22)
Platform Flash (U27)
Ethernet
DVI Output
BPI Flash (U4)
X8 PCI Express
Kit Contents
• ML605 board and FMC Connectivity Daughter Card
• CX4 Loopback Connector
• Universal 12V power supply
• 2 USB A / Mini-B cables
• 1 ethernet Cat5 cable
• 1 DVI-to-VGA adapter
• Four SMA cables
• 1 SATA cable, 1 SATA loopback cable
• 1 CompactFlash card (2GB)
• Xilinx ISE Design Suite DVDs - 1 1.1 and 1 1.4 Update
• 1 USB stick
• Fedora Core 10 Live CD
• Documents include a welcome letter, Hardware Setup Guide,
Getting Started Guide
VIRTEX-6 FPGA CONNECTIVITY KIT
For More I n ForMatIon Go to
www.xI lI nx.coM/V6con n KIt
FMC (HPC) System ACE
Connectivity Daughter Card
Switch S2
USB 2.0 12V ATX Power
(Host)
USB 2.0
Switch S1
12V Wall Power (Device)
Prog (SW4)
SystemACE RST (SW3)
CPU RST (SW10)
PMBus Controller
System Monitor Headers
PMBus (J3)
16x2 LCD Character Display
Push Buttons (SW5-SW9)
MGT Port (J26-J29)
What's Needed for Demonstration
• Xilinx Virtex-6 FPGA Connectivity Kit
• PC system with a x8/x16 PCIe slot on the motherboard, CDROM
drive and a USB port
• Keyboard & Mouse
• Monitor