Xilinx Virtex-6 Manual page 356

Chapter 4: About Design Elements
SIM_CONFIG_V6
Simulation: Configuration Simulation Model
Introduction
This simulation component allows the functional simulation of many of the common configuration interface,
functions and commands to assist with board-level understanding and debug of configuration behaviors. The
model can also simulate some startup-up behaviors such as the global set/reset (GSR) and global 3-state (GTS)
assertion in the design. This model does not map to a specific primitive in the FPGA software and cannot be
directly instantiated in the design, however it can be used in conjunction with the source design if specified either
in a simulation-only file like a testbench or by some means guarded from synthesis so that it is not synthesized
into the design netlist. This model may be used for either functional (RTL) simulation or timing simulation.
This model is also indirectly used when instantiating the ICAP_VIRTEX6 in simulating configuration access to
that component.
Port Descriptions
Port Direction
Output
BUSY
Output
CSOB
DONE Inout
CCLK Input
CSIB Input
D Input
INITB Input
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Width Function
1
This output pin is used during read back.
1
Parallel daisy-chain active-Low chip select output. Not used in
single FPGA applications.
1 Active-High signal indicating configuration is complete:
• 0 = FPGA not configured
• 1 = FPGA configured
1
Configuration clock source for all configuration modes except JTAG.
1
Active-Low chip select to enable the SelectMAP data bus:
• 0 = SelectMAP data bus enabled
• 1 = SelectMAP data bus disabled
32
Configuration and read back data bus, clocked on the rising edge of
CCLK.
1 Before the Mode pins are sampled, INIT_B is an input that can be
held Low to delay configuration. After the Mode pins are sampled,
INIT_B is an open-drain, active-Low output indicating whether a
CRC error occurred during configuration:
• 0 = CRC error
• 1 = No CRC error
When the SEU detection function is enabled, INIT_B is optionally
driven Low when a read back CRC error is detected.
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013