Xilinx Virtex-6 Manual page 250

Chapter 4: About Design Elements
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute
BANDWIDTH
CLKFBOUT_MULT_F
CLKFBOUT_PHASE
CLKIN_PERIOD
CLKOUT0_DIVIDE_F
CLKOUT[0:6]_DIVIDE
CLKOUT[0:6]_DUTY_
CYCLE
CLKOUT[0:6]_
PHASE
CLKOUT4_CASCADE
250
Allowed
Data Type Values
String "OPTIMIZED",
"HIGH",
"LOW"
3 5.0 to
significant 64.0
digit Float
3 -360.000 to
significant 360.000
digit Float
1.000 to
Float (nS)
100.000
3 1.000 to
significant 128.000
digit Float
Integer 1 to 128
3 0.001 to
significant 0.999
digit Float
3 -360.000 to
significant 360.000
digit Float
Boolean FALSE, TRUE
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Yes
No
Recommended
No
Default Description
"OPTIMIZED" Specifies the MMCM programming
algorithm affecting the jitter, phase margin,
and other characteristics of the MMCM.
5.0 Specifies the amount to multiply
all CLKOUT clock outputs if a
different frequency is desired. This
number, in combination with the
associated CLKOUT#_DIVIDE value and
DIVCLK_DIVIDE value, will determine the
output frequency. Even though this value
needs to be specified as a real number, only
whole integer values are supported. For
example, 6.0 is OK but 6.5 is not.
0.000
Specifies the phase offset in degrees of the
clock feedback output. Shifting the feedback
clock results in a negative phase shift of all
output clocks to the MMCM.
0.000
Specifies the input period in ns to the
MMCM CLKIN1 input. Resolution is down
to the ps. This information is mandatory
and must be supplied.
1.000
Specifies the amount to divide the
associated CLKOUT clock output if a
different frequency is desired. This number
in combination with the CLKFBOUT_MULT
and DIVCLK_DIVIDE values will determine
the output frequency.
1
Specifies the amount to divide the
associated CLKOUT clock output if a
different frequency is desired. This number
in combination with the CLKFBOUT_MULT
and DIVCLK_DIVIDE values will determine
the output frequency.
0.500
Specifies the Duty Cycle of the associated
CLKOUT clock output in percentage (i.e.,
0.50 will generate a 50% duty cycle).
0.000 Specifies the phase offset in degrees of the
clock feedback output. Shifting the feedback
clock results in a negative phase shift of all
output clocks to the MMCM.
FALSE Cascades the output divider (counter) into
the input of the CLKOUT4 divider for an
output clock divider that is greater than 128.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013