Xilinx Virtex-6 Manual page 295

RAM128X1D
Primitive: 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM)
Introduction
This design element is a 128-bit deep by 1-bit wide random access memory and has a read/write port that writes
the value on the D input data pin when the write enable (WE) is high to the location specified by the A address
bus. This happens shortly after the rising edge of the WCLK and that same value is reflected in the data output
SPO. When WE is low, an asynchronous read is initiated in which the contents of the memory location specified
by the A address bus is output asynchronously to the SPO output. The read port can perform asynchronous
read access of the memory by changing the value of the address bus DPRA, and by outputing that value to the
DPO data output.
Port Descriptions
Port Direction
SPO Output
DPO Output
D Input
A Input
Input
DPRA
Input
WE
Input
WCLK
If instantiated, the following connections should be made to this component:
• Tie the WCLK input to the desired clock source, the D input to the data source to be stored and the DPO
output to an FDCE D input or other appropriate data destination.
• Optionally, the SPO output can also be connected to the appropriate data destination or else left unconnected.
• The WE clock enable pin should be connected to the proper write enable source in the design.
• The 7-bit A bus should be connected to the source for the read/write addressing and the 7-bit DPRA bus
should be connected to the appropriate read address connections.
• An optional INIT attribute consisting of a 128-bit Hexadecimal value can be specified to indicate the initial
contents of the RAM.
If left unspecified, the initial contents default to all zeros.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
Width Function
1
Read/Write port data output addressed by A
1
Read port data output addressed by DPRA
1
Write data input addressed by A
7
Read/Write port address bus
7
Read port address bus
1
Write Enable
1
Write clock (reads are asynchronous)
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Chapter 4: About Design Elements
295