Xilinx Virtex-6 FPGA User Manual
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Xilinx Virtex-6 FPGA User Manual

Xilinx Virtex-6 FPGA User Manual

System monitor
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Virtex-6 FPGA
System Monitor
User Guide
UG370 (v1.1) June 14, 2010
www.BDTIC.com/XILINX

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Summary of Contents for Xilinx Virtex-6 FPGA

  • Page 1 Virtex-6 FPGA System Monitor User Guide UG370 (v1.1) June 14, 2010 www.BDTIC.com/XILINX...

  • Page 2: Revision History

    Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates.

  • Page 3: Table Of Contents

    ..........6 Virtex-6 FPGA System Monitor System Monitor Primitive .
  • Page 4 ChipScope Pro Tool and System Monitor ........60 www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 5: Preface: About This Guide

    Virtex-6 Family Overview The features and product selection of the Virtex-6 family are outlined in this overview. • Virtex-6 FPGA Data Sheet: DC and Switching Characteristics This data sheet contains the DC and Switching Characteristic specifications for the Virtex-6 family.

  • Page 6: Additional Support Resources

    Additional Support Resources To search the database of silicon and software questions and answers or to create a technical support case in WebCase, see the Xilinx website at: http://www.xilinx.com/support. For the most up to date support information including software updates, reference designs, tutorials, and FAQs please got to: http://www.xilinx.com/systemmonitor...

  • Page 7: Virtex-6 Fpga System Monitor

    Virtex-6 FPGA System Monitor Every member of the Virtex®-6 FPGA family contains a single System Monitor, which is located in the center of every die. The System Monitor function is built around a 10-bit, 200-kSPS (kilosamples per second) Analog-to-Digital Converter (ADC). When combined with a number of on-chip sensors, the ADC is used to measure FPGA physical operating parameters like on-chip power supply voltages and die temperatures.

  • Page 8: System Monitor Primitive

    System Monitor is instantiated in a design (see Register File Interface, page 14). For the latest information, including FAQs, software updates, and tutorials, refer to http://www.xilinx.com/systemmonitor. System Monitor Primitive System Monitor Ports Figure 2 illustrates the ports on the primitive (SYSMON) used to instantiate System Monitor in a design.
  • Page 9 BUSY Output ADC busy signal. This signal transitions High during an ADC conversion. This signal also transitions High for an extended period during an ADC or Supply Sensor calibration. www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...

  • Page 10: User Attributes

    Holding INIT_B or PROG Low to delay configuration has no effect on System Monitor. System Monitor is available as soon as the Clear Configuration Memory step is complete, which is normally indicated by INIT_B going High. See the “Configuration Sequence” section in the Virtex-6 FPGA Configuration Guide for more information.

  • Page 11: Analog-To-Digital Converter

    Analog-to-Digital Converter The ADC is used to digitize the output of the on-chip sensors and voltages connected to the external analog inputs. The ADC specifications are listed in the Virtex-6 FPGA Data Sheet. The System Monitor ADC carries out a 16-bit resolution conversion of all sensor and external analog input voltages.

  • Page 12: Temperature Sensor

    (AGND). This internal reference is typically less accurate over REFP a wide temperature range than an external reference. Performance using the internal reference circuit is specified in the Virtex-6 FPGA Data Sheet. For the most accurate measurements, an external reference IC is recommended. The remaining analog pins (AV...
  • Page 13 14). The full ADC transfer function describes temperatures outside the FPGA operating temperature range. This does not mean that the FPGA is operational at these temperatures (refer to Virtex-6 FPGA Data Sheet for temperature specifications). System Monitor is operational over a temperature range of –40°C to +125°C on all parts irrespective of grade.

  • Page 14: Power Supply Sensor

    DRP. The DRP timing is shown in Figure 16, page 38. For a detailed description of the DRP timing please refer to the Virtex-6 FPGA Configuration Guide. For more information on the JTAG DRP interface, see DRP JTAG Interface, page www.BDTIC.com/XILINX...

  • Page 15: Status Registers

    The status registers also store the maximum and minimum measurements recorded for the on-chip sensors from the chip power-up or the last user reset of the System Monitor logic. Table 3 for a list of the status registers and definitions. www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...
  • Page 16 CCINT CCINT - bit data MSB justified. - up or the last SYSMON reset. Min V Minimum V measurement recorded since power CCAUX CCAUX - bit data MSB justified. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 17: Flag Register

    The configuration registers are modifiable through the DRP after the FPGA has been configured. For example, a soft microprocessor or state machine can be used to alter the contents of the System Monitor control registers at any time during normal operation. www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...
  • Page 18 This bit is used in Single Channel mode to select either Unipolar or Bipolar operating mode for the ADC analog inputs (see Analog Inputs, page 39). A logic High places the ADC in differential mode and logic 0 places the ADC in unipolar mode. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...
  • Page 19 1. These channel selection options are used for System Monitor self-check and calibration operations. When these channels are selected, the supply sensor is connected to V and V REFP REFN www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...

  • Page 20: Test Registers (43H To 47H)

    Test Registers (43h to 47h) These registers are intended for factory test purposes only and have a default status of zero. The user must not write to these registers. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 21: Channel Sequencer Registers (48H To 4Fh)

    SYSMON has been added to Virtex-6 devices to allow access to the System Monitor DRP through the JTAG TAP. All System Monitor JTAG instructions are 32-bits in length. For more information on the Virtex-6 FPGA Boundary-Scan instructions and usage, see the Virtex-6 FPGA Configuration Guide. Read and Write operations using the System Monitor JTAG DRP interface are described in the next sections.

  • Page 22: System Monitor Jtag Drp Read Operation

    Figure 11. Thus, as the result of a read operation is being shifted out of the SYSMON DR, an instruction for the next read can be shifted in. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 23: Jtag Drp Commands

    System Monitor Data Register (SYSMON DR) UG370_12_060809 Figure 12: SYSMON JTAG DRP Command Table 12: JTAG DRP Commands CMD[3:0] Operation No operation DRP Read DRP Write – – – – Not defined www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...

  • Page 24: Drp Arbitration

    The signal remains High until the port is unlocked again. No read or write access is possible via the DRP fabric port when the JTAGLOCKED signal is High. The www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 25: System Monitor Control Logic

    Sequencer registers. It is recommended the System Monitor is placed in safe mode by writing zeros to SEQ0 and SEQ1 while updating the Control Registers. System Monitor is automatically reset whenever SEQ1 and SEQ0 are changed. The current status register www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...

  • Page 26: Adc Channel Selection (48H And 49H)

    Table 14: Sequencer ADC Channel Selection, Control Register 49h Sequence Description Number Channel VAUXP[0],VAUXN[0]—Auxiliary channel 1 VAUXP[1],VAUXN[1]—Auxiliary channel 2 VAUXP[2],VAUXN[2]—Auxiliary channel 3 VAUXP[3],VAUXN[3]—Auxiliary channel 4 www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 27: Adc Channel Averaging (4Ah And 4Bh)

    If averaging is enabled for the calibration channel (by setting CAVG logic Low), the coefficients will be updated after the first pass through the sequence. Subsequent updates to coefficient registers will require 16 conversions before the coefficients are updated. www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...
  • Page 28 Enable averaging—VAUXP[6],VAUXN[6]—Auxiliary channel 7 Enable averaging—VAUXP[7],VAUXN[7]—Auxiliary channel 8 Enable averaging—VAUXP[8],VAUXN[8]—Auxiliary channel 9 Enable averaging—VAUXP[9],VAUXN[9]—Auxiliary channel 10 Enable averaging—VAUXP[10],VAUXN[10]—Auxiliary channel 11 Enable averaging—VAUXP[11],VAUXN[11]—Auxiliary channel 12 Enable averaging—VAUXP[12],VAUXN[12]—Auxiliary channel 13 Enable averaging—VAUXP[13],VAUXN[13]—Auxiliary channel 14 www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 29: Adc Channel Analog-Input Mode (4Ch And 4Dh)

    The limits written to the threshold registers are MSB justified. Limits are derived from the temperature and power-supply sensor transfer functions (see Figure 5, page 13 Figure 6, page 14). www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...

  • Page 30: Supply Sensor Alarms

    FPGA enters power down approximately 10 ms later. The power-down feature initiates a configuration shutdown sequence disabling the device when finished and asserts GHIGH to prevent any contention (see Virtex-6 FPGA Configuration Guide). When OT is deasserted, GHIGH will also deassert and the startup sequence is initiated releasing all global resources.

  • Page 31: Thermal Diode (Dxp And Dxn)

    < 2 Ω . For implementation details, consult the data sheet for the selected external thermal monitoring IC. System Monitor Calibration The Virtex-6 FPGA System Monitor can digitally calibrate out any offset-and-gain errors in the ADC and supply sensor (see Calibration Coefficients for an explanation of offset and gain errors).

  • Page 32: Calibration Coefficients

    0V (where the transfer function crosses the y axis). This offset is removed by digitally subtracting this offset. The result of this offset calibration is shown in Figure 13 by the blue dashed line. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 33: System Monitor Timing

    Table 19, page 39 describes the timing parameters. Reference the Virtex-6 FPGA Data Sheet for the latest System Monitor timing specifications. The robust nature of the System Monitor ensures continued and correct operation even if the external clock input DCLK is stopped. In this situation, the System Monitor automatically switches www.BDTIC.com/XILINX...

  • Page 34: Continuous Sampling

    Sequencer, page 25). For more information on the effects of source impedance on the acquisition, see Analog Input Description. Figure 14, ADCCLK is an internal clock used by the ADC. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 35: Conversion Phase

    System Monitor’s EOS signal has the same timing as EOC. This signal is pulsed when the output data register for the last channel in a programmed channel sequence is updated. www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...

  • Page 36: Event-Driven Sampling

    If System Monitor is reset while operating in event mode, the first conversion result is valid on an EOC pulse following the first CONVST pulse after RESET is released. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...
  • Page 37 Conversion Time ADCCLK N th Sampling Edge N th Conversion Finished BUSY CONVST EOC / EOS CHANNEL[4:0] N-1 Channel Selection N Selection UG370_15_060809 Figure 15: Event Driven Sampling Mode Timing www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...
  • Page 38 Table 19 describes the timing events shown in Figure X-Ref Target - Figure 16 DCLK DADDR[6:0] DI[15:0] DO[15:0] DRDY EOC/EOS ALM[2:0]/OT BUSY CHANNEL[4:0] UG370_16_060809 Figure 16: System Monitor Detailed Timing www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 39: Analog Inputs

    High. The data is in placed in the DRP register three DCLK cycles later. DRDY goes High when the data has been written. See the Dynamic Reconfiguration Port description in the Virtex-6 FPGA Configuration Guide for more information. 4. For a DRP read operation, address on DADDR[6:0] is latched on the rising edge of DCLK when DEN is High, and three DCLK cycles later the data is placed on the DO bus.

  • Page 40: Auxiliary Analog Inputs

    The System Monitor auxiliary input pins are defined in Virtex-6 FPGA Packaging and Pinout Specification as _SMxP_ and _SMxN_, where x is the auxiliary pair number. For example, the auxiliary input V [15] is designated IO_L10P_CC_SM15P_11 in the pinout specification.

  • Page 41: Adjusting The Acquisition Time

    I/O is used as a digital I/O, it is subject to the specifications of the I/O standard for that pin. If the I/O is used as an analog input, the input voltage must adhere to the specifications given in the “Analog-to-Digital Converter” section of the Virtex-6 FPGA Data Sheet.

  • Page 42: Unipolar Input Signals

    X-Ref Target - Figure 19 2.5V 0V to 1V Peak voltage on V 1.5V Common Voltage 0V to 0.5V 0.5V Common Mode Range (Common Mode) UG370_19_060809 Figure 19: Unipolar Analog-Input Range www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 43: Bipolar Input Signals

    ) should not exceed ±100 mV. X-Ref Target - Figure 21 ±0.5V – ±0.1V 2.5V = ±0.1V 1.5V = 1V 0.5V – 1V = ±0.5V 0.5V = 0.5V UG370_21_060809 Figure 21: Differential Analog-Input Range www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...
  • Page 44 1 LSB = 1V / 1024 = 0.977 µV 002h 001h 000h 3FFh 3FEh 3FDh 201h 200h -2 -1 +1 +2 -500 +499 Input Voltage (mV) UG370_23_060809 Figure 23: Bipolar Transfer Function www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 45: Application Guidelines

    Application Guidelines Application Guidelines The Virtex-6 FPGA System Monitor is a precision analog measurement system based on a 10-bit Analog-to-Digital Converter (ADC) with an LSB size that is approximately equal to 1 mV. To achieve the best possible performance and accuracy with all measurements (both on-chip and external), a number of dedicated pins for the ADC reference and power supply are provided.
  • Page 46 DC return current. X-Ref Target - Figure 25 Z , R, and X vs Frequency 1200 1000 1000 10000 Frequency (MHz) UG370_25_060809 Figure 25: Ferrite Impedance Versus Frequency Plot www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 47: External Analog Inputs

    These routing channels can be used to bring tightly coupled differential pairs into the center of the via field—even when using 5 mil tolerances. www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...
  • Page 48 ) are routed as a tightly coupled differential pair from an external 1.25V reference IC REFN at the bottom edge of the FPGA (refer to Figure 24, page 46 for the connections). The www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 49: Example Instantiation Of Sysmon

    By varying the V supply on the board, the alarm can be CCAUX triggered or the varying supply voltage can be monitored on the DO bus. www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...

  • Page 50: Sysmon I/O

    VCCAUX is the last channel in the sequence, allowing EOS to be used as an input to DEN to latch the address on DADDR[6:0] and enable the contents of Status register 02h onto the DO bus for reading. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 51: Sysmon Attributes

    (refer to ADC Channel Selection (48h and 49h), page INIT_49 0000h INIT_4A Enable Averaging on the V channel (refer to 0400h CCAUX Channel Averaging (4Ah and 4Bh), page INIT_4B 0000h www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...
  • Page 52 Figure 6. The limit can be calculated as (Limit/3V) * 2 . Therefore (2.375/3) * 2 = 51882 or CAAAh. www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...
  • Page 53 //////////////////////////////////////////////////////////////////////// // Author: Xilinx // Date: July 11th 2007 $ // Design: Virtex-6 FPGA System Monitor Verilog example instantiation // System Monitor instantiation by hand using the Language Template //////////////////////////////////////////////////////////////////////// `timescale 1ns / 1 ps module v5_sysmon // Inputs clk,...
  • Page 54 // 1-bit input clock for dynamic reconfig port .DEN(eos), // 1-bit input enable for dynamic reconfig port .DWE(1'b0), // 1-bit input write enable for dynamic reconfig port .RESET(1'b0) // 1-bit input active high reset endmodule www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...
  • Page 55 Example Instantiation using VHDL ---------------------------------------------------------------------------------- -- Author: Xilinx -- Date: July 11th 2007 $ -- Design: Virtex-6 FPGA System Monitor VHDL example instantiation -- System Monitor instantiation by hand using the Language Template ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;...
  • Page 56 BUSY => busy, ALM => alm, RESET=> '0', CONVST => '0', CONVSTCLK => '0', DI => "0000000000000000", VAUXN => "0000000000000000", VAUXP=> "0000000000000000", VN => '0', VP => '0' end Behavioral; www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

  • Page 57: Simulation Of The Sysmon Design

    Application Guidelines Simulation of the SYSMON Design A behavioral simulation model is provided for the Virtex-6 FPGA System Monitor. This model allows the user to simulate most of the System Monitor functionality and timing. The simulation model also allows users to easily introduce analog signals into their design without the need for mixed mode or analog simulation capability in their tools.
  • Page 58 The DRDY signal goes High to indicate valid data is on the bus. Notice how the alarm signal goes High before the EOS signal is pulsed. The VHDL and Verilog projects for this example can be downloaded from the Xilinx website at ug192.zip.

  • Page 59: Edk Support For System Monitor

    EDK Support for System Monitor An Analog-to-Digital Converter (ADC) is a common microprocessor peripheral. Starting with EDK 9.2i software, the Xilinx Embedded Development Kit (EDK) includes IP that allows designers to easily connect System Monitor to the Processor Local Bus (PLB). The IP is also supported with software drivers that allow application code to be quickly developed.

  • Page 60: Chipscope Pro Tool And System Monitor

    Application Guidelines ChipScope Pro Tool and System Monitor A useful feature of the Virtex-6 FPGA System Monitor is the ability to access the measurement information via the JTAG TAP at any time—even before the FPGA is configured. Most PC boards have an existing JTAG infrastructure that is used for debugging and testing the hardware.
  • Page 61 Application Guidelines X-Ref Target - Figure 34 UG370_34_060809 Figure 34: System Monitor JTAG Access using ChipScope Pro Tool www.BDTIC.com/XILINX Virtex-6 FPGA System Monitor www.xilinx.com UG370 (v1.1) June 14, 2010...
  • Page 62 Application Guidelines www.BDTIC.com/XILINX www.xilinx.com Virtex-6 FPGA System Monitor UG370 (v1.1) June 14, 2010...

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