Xilinx Virtex-6 Manual page 140

Chapter 4: About Design Elements
FRAME_ECC_VIRTEX6
Primitive: Virtex®-6 Configuration Frame Error Detection and Correction Circuitry
Introduction
This design element enables the dedicated, built-in ECC (Error Detection and Correction Circuitry) for the
configuration memory of the FPGA. This element contains outputs that allow monitoring of the status of the ECC
circuitry and the status of the readback CRC circuitry.
SEU Correction feature provides hardware version to allow automatic correction of single-bit errors. New
additional outputs used by the correction feature include the decoding of the Hamming code syndrome
for use by the soft core.
Port Descriptions
Port
CRCERROR
ECCERROR
ECCERRORSINGLE
FAR[23:0]
SYNBIT[4:0]
SYNDROME[12:0]
SYNDROMEVALID
SYNWORD[6:0]
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
140
Direction Width Function
Output 1 Output indicating a CRC error.
Output 1 Output indicating a ECC error.
Output 1 Indicates single-bit Frame ECC error detected.
Output 24 Frame Address Register Value.
Output 5 Bit address of error.
Output 13 Output location of erroneous bit
Output 1 Frame ECC output indicating the SYNDROME output is valid.
Output 7 Word in the frame where an ECC error has been detected.
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Recommended
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013