Xilinx Virtex-6 Manual page 262

Chapter 4: About Design Elements
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- MUXF7: CLB MUX to tie two LUT6's together with general output
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
MUXF7_inst : MUXF7
port map (
O => O, -- Output of MUX to general routing
I0 => I0, -- Input (tie to MUXF6 LO out or LUT6 O6 pin)
I1 => I1, -- Input (tie to MUXF6 LO out or LUT6 O6 pin)
S => S -- Input select to MUX
);
-- End of MUXF7_inst instantiation
Verilog Instantiation Template
// MUXF7: CLB MUX to tie two LUT6's together with general output
// Virtex-6
// Xilinx HDL Libraries Guide, version 14.5
MUXF7 MUXF7_inst (
.O(O), // Output of MUX to general routing
.I0(I0), // Input (tie to LUT6 O6 pin)
.I1(I1), // Input (tie to LUT6 O6 pin)
.S(S) // Input select to MUX
);
// End of MUXF7_inst instantiation
For More Information
See the Virtex-6 FPGA User Documentation (User Guides and Data
262
Sheets).
Virtex-6 Libraries Guide for HDL Designs
www.xilinx.com UG623 (v 14.5) March 20, 2013