Xilinx Virtex-6 Manual page 286

Chapter 4: About Design Elements
Available Attributes
Data
Attribute Type
DATA_RATE_OQ String
DATA_RATE_TQ String
DATA_WIDTH Integer
DDR3_DATA Integer
INIT_OQ Binary
INIT_TQ Binary
INTERFACE_TYPE String
Integer
ODELAY_USED
SERDES_MODE String
SRVAL_OQ Binary
SRVAL_TQ Binary
TRISTATE_WIDTH Integer
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- OSERDESE1: Output SERial/DESerializer
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
OSERDESE1_inst : OSERDESE1
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
DDR3_DATA => 1,
286
Allowed Values Default
"DDR", "SDR" "DDR"
"DDR", "DDR"
"BUF",
"SDR"
4, 2, 3, 5, 6, 7, 8, 10 4
1, 0 1
1'b0 to 1'b1 1'b0
1'b0 to 1'b1 1'b0
"DEFAULT", "DEFAULT"
"MEMORY_DDR3"
0, 1 0
"MASTER", "MASTER"
"SLAVE"
1'b0 to 1'b1 1'b0
1'b0 to 1'b1 1'b0
4, 1 4
-- "SDR" or "DDR"
-- "BUF", "SDR" or "DDR"
-- Parallel data width (1-8,10)
-- Must leave at 1 (MIG-only parameter)
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Description
Defines whether data (OQ) changes at every
clock edge or every positive clock edge with
respect to CLK.
Defines whether the 3-state (TQ) changes at
every clock edge, every positive clock edge with
respect to clock, or is set to buffer configuration.
Defines the parallel-to-serial data converter
width. This value also depends on the
DATA_RATE_OQ value.If DATA_RATE_OQ
= DDR, value is limited to 4, 6, 8, or 10. If
DATA_RATE_OQ = SDR, value is limited to 2, 3,
4, 5, 6, 7, or 8.
For DDR3, if the I/O is a DQ or DQS pin, set to 1.
If control, address, clock, etc. set to 0.
Defines the initial value of OQ output.
Defines the initial value of TQ output.
Chooses OSERDESE1 use model.
ODELAY_USED attribute is only for DDR3 mode.
This attribute helps to set the output circular
buffer in the correct mode when using ODELAY.
Set ODELAY_USED to 0 for all other modes, even
when ODELAY is used in the design.
Defines whether the OSERDES module is a
master or slave when using width expansion.
Defines the value of OQ outputs when the SR is
invoked.
Defines the value of TQ outputs when the SR is
invoked.
Defines the parallel to serial 3-state
converter width. If DATA_RATE_TQ =
DDR, DATA_WIDTH = 4, and DATA_RATE_OQ
= DDR, value is limited to 1 or 4. For all other
settings of DATA_RATE_TQ, DATA_WIDTH,
and DATA_RATE_OQ, value is limited to 1.
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013