Xilinx Virtex-6 Manual page 256

Chapter 4: About Design Elements
Port
LOCKED
PWRDWN
RST
Design Entry Method
Instantiation
Inference
CORE Generator™ and wizards
Macro support
Available Attributes
Attribute
BANDWIDTH
CLKFBOUT_MULT_F
CLKFBOUT_PHASE
CLKIN1_PERIOD
CLKOUT0_DIVIDE_F
CLKOUT[0:6]_DUTY_
CYCLE
256
Direction Width
Output 1
Input 1
Input 1
Allowed
Data Type Values
String "OPTIMIZED",
"HIGH",
"LOW"
5.0 to
3 significant
digit Float 64.0
3 significant -360.000 to
digit Float 360.000
Float (nS) 1.000 to
1000.000
3 significant 1.000 to
128.000
digit Float
3 significant 0.001 to
0.999
digit Float
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Function
An output from the MMCM that indicates when the MMCM
has achieved phase alignment within a predefined window and
frequency matching within a predefined PPM range. The MMCM
automatically locks after power on. No extra reset is required.
LOCKED will be deasserted if the input clock stops or the phase
alignment is violated (e.g., input clock phase shift). The MMCM
automatically reacquires lock after LOCKED is deasserted.
Powers down instantiated but unused MMCMs.
Asynchronous reset signal. The MMCM will synchronously
re-enable itself when this signal is released (i.e., MMCM
re-enabled). A reset is not required when the input clock
conditions change (e.g., frequency).
Yes
No
Recommended
No
Default Description
"OPTIMIZED" Specifies the MMCM programming
algorithm affecting the jitter, phase margin,
and other characteristics of the MMCM.
5.0
Specifies the amount to multiply
all CLKOUT clock outputs if a
different frequency is desired. This
number, in combination with the
associated CLKOUT#_DIVIDE value and
DIVCLK_DIVIDE value, will determine the
output frequency.
0.000 Specifies the phase offset in degrees of
the clock feedback output. Shifting the
feedback clock results in a negative phase
shift of all output clocks to the MMCM.
0.000 Specifies the input period in ns to the
MMCM CLKIN1 input. Resolution is down
to the ps. This information is mandatory
and must be supplied.
1.000 Specifies the amount to divide the
associated CLKOUT clock output if a
different frequency is desired. This number
in combination with the CLKFBOUT_MULT
and DIVCLK_DIVIDE values will determine
the output frequency.
0.500 Specifies the Duty Cycle of the associated
CLKOUT clock output in percentage (for
instance, 0.50 will generate a 50% duty
cycle).
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013