Xilinx Virtex-6 Manual page 248

Chapter 4: About Design Elements
MMCM_ADV
Primitive: MMCM is a mixed signal block designed to support clock network deskew,
frequency synthesis, and jitter reduction.
Introduction
The MMCM is a mixed signal block designed to support frequency synthesis, clock network deskew, and jitter
reduction. The clock outputs can each have an individual divide, phase shift and duty cycle based on the same
VCO frequency. Additionally, the MMCM supports dynamic phase shifting and fractional divides.
Port Descriptions
Port
CLKFBIN
CLKFBOUT
CLKFBOUTB
CLKFBSTOPPED
248
Direction Width Function
Input 1 Feedback clock input.
Output 1 Dedicated MMCM feedback output.
Output 1 Inverted CLKFBOUT.
Output 1 Status pin indicating that the feedback clock has stopped.
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Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013