Xilinx Virtex-6 Manual page 81

BUFGCE_1
Primitive: Global Clock Buffer with Clock Enable and Output State 1
Introduction
This design element is a multiplexed global clock buffer with a single gated input. Its O output is High (1) when
clock enable (CE) is Low (inactive). When clock enable (CE) is High, the I input is transferred to the O output.
Logic Table
Inputs
I
X
I
Port Descriptions
Port
I
CE
O
Design Entry Method
Instantiation
Inference
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Macro support
VHDL Instantiation Template
Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
-- BUFGCE_1: Global Clock Buffer with Clock Enable and Output State 1
-- Virtex-6
-- Xilinx HDL Libraries Guide, version 14.5
BUFGCE_1_inst : BUFGCE_1
port map (
O => O, -- 1-bit output: Clock buffer output
CE => CE, -- 1-bit input: Clock enable input for I0 input
I => I -- 1-bit input: Primary clock input
);
Virtex-6 Libraries Guide for HDL Designs
UG623 (v 14.5) March 20, 2013
CE
0
1
Direction
Input
Input
Output
www.xilinx.com
Chapter 4: About Design Elements
Outputs
O
1
I
Width
1
1
1
Yes
Recommended
No
No
Function
Clock buffer input
Clock enable input
Clock buffer output
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